now register_driver and register_device are for bus only usage. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
320 lines
7.6 KiB
C
320 lines
7.6 KiB
C
/*
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* Driver for Atmel AT32 and AT91 SPI Controllers
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*
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* Copyright (C) 2011 Hubert Feurstein <h.feurstein@gmail.com>
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*
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* based on imx_spi.c by:
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* Copyright (C) 2008 Sascha Hauer, Pengutronix
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*
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* based on atmel_spi.c from the linux kernel by:
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* Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <errno.h>
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#include <clock.h>
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#include <xfuncs.h>
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#include <gpio.h>
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#include <io.h>
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#include <spi/spi.h>
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#include <mach/io.h>
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#include <mach/board.h>
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#include <mach/cpu.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include "atmel_spi.h"
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struct atmel_spi {
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struct spi_master master;
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void __iomem *regs;
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struct clk *clk;
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int *cs_pins;
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};
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#define to_atmel_spi(p) container_of(p, struct atmel_spi, master)
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#define SPI_XCHG_TIMEOUT (100 * MSECOND)
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/*
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* Version 2 of the SPI controller has
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* - CR.LASTXFER
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* - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
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* - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
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* - SPI_CSRx.CSAAT
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* - SPI_CSRx.SBCR allows faster clocking
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*
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* We can determine the controller version by reading the VERSION
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* register, but I haven't checked that it exists on all chips, and
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* this is cheaper anyway.
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*/
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static inline bool atmel_spi_is_v2(void)
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{
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return !cpu_is_at91rm9200();
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}
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static int atmel_spi_setup(struct spi_device *spi)
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{
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struct spi_master *master = spi->master;
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struct atmel_spi *as = to_atmel_spi(master);
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u32 scbr, csr;
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unsigned int bits = spi->bits_per_word;
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unsigned long bus_hz;
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if (spi->controller_data) {
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csr = (u32)spi->controller_data;
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spi_writel(as, CSR0, csr);
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return 0;
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}
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dev_dbg(master->dev, "%s mode 0x%08x bits_per_word: %d speed: %d\n",
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__func__, spi->mode, spi->bits_per_word,
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spi->max_speed_hz);
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bus_hz = clk_get_rate(as->clk);
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if (!atmel_spi_is_v2())
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bus_hz /= 2;
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if (spi->max_speed_hz) {
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/*
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* Calculate the lowest divider that satisfies the
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* constraint, assuming div32/fdiv/mbz == 0.
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*/
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scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
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/*
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* If the resulting divider doesn't fit into the
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* register bitfield, we can't satisfy the constraint.
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*/
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if (scbr >= (1 << SPI_SCBR_SIZE)) {
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dev_dbg(master->dev,
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"setup: %d Hz too slow, scbr %u; min %ld Hz\n",
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spi->max_speed_hz, scbr, bus_hz/255);
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return -EINVAL;
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}
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} else {
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/* speed zero means "as slow as possible" */
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scbr = 0xff;
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}
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csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
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if (spi->mode & SPI_CPOL)
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csr |= SPI_BIT(CPOL);
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if (!(spi->mode & SPI_CPHA))
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csr |= SPI_BIT(NCPHA);
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/* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
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*
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* DLYBCT would add delays between words, slowing down transfers.
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* It could potentially be useful to cope with DMA bottlenecks, but
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* in those cases it's probably best to just use a lower bitrate.
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*/
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csr |= SPI_BF(DLYBS, 0);
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csr |= SPI_BF(DLYBCT, 0);
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/* gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH)); */
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dev_dbg(master->dev,
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"setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
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bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
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spi_writel(as, CSR0, csr);
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/*
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* store the csr-setting when bits are defined. This happens usually
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* after the specific spi_device driver has been probed.
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*/
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if (bits > 0)
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spi->controller_data = (void *)csr;
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return 0;
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}
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static void atmel_spi_chipselect(struct spi_device *spi, struct atmel_spi *as, int on)
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{
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struct spi_master *master = &as->master;
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int cs_pin;
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int val = ((spi->mode & SPI_CS_HIGH) != 0) == on;
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BUG_ON(spi->chip_select >= master->num_chipselect);
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cs_pin = as->cs_pins[spi->chip_select];
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gpio_direction_output(cs_pin, val);
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}
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static int atmel_spi_xchg(struct atmel_spi *as, u32 tx_val)
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{
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uint64_t start;
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start = get_time_ns();
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while (!(spi_readl(as, SR) & SPI_BIT(TDRE))) {
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if (is_timeout(start, SPI_XCHG_TIMEOUT)) {
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dev_err(as->master.dev, "tx timeout\n");
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return -ETIMEDOUT;
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}
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}
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spi_writel(as, TDR, tx_val);
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start = get_time_ns();
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while (!(spi_readl(as, SR) & SPI_BIT(RDRF))) {
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if (is_timeout(start, SPI_XCHG_TIMEOUT)) {
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dev_err(as->master.dev, "rx timeout\n");
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return -ETIMEDOUT;
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}
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}
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return spi_readl(as, RDR) & 0xffff;
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}
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static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *mesg)
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{
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int ret;
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struct spi_master *master = spi->master;
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struct atmel_spi *as = to_atmel_spi(master);
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struct spi_transfer *t = NULL;
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unsigned int bits = spi->bits_per_word;
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mesg->actual_length = 0;
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ret = master->setup(spi);
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if (ret < 0) {
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dev_dbg(master->dev, "transfer: master setup failed\n");
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return ret;
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}
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dev_dbg(master->dev, " csr0: %08x\n", spi_readl(as, CSR0));
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#ifdef VERBOSE
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list_for_each_entry(t, &mesg->transfers, transfer_list) {
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dev_dbg(master->dev,
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" xfer %p: len %u tx %p rx %p\n",
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t, t->len, t->tx_buf, t->rx_buf);
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}
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#endif
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atmel_spi_chipselect(spi, as, 1);
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list_for_each_entry(t, &mesg->transfers, transfer_list) {
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u32 tx_val;
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int i = 0, rx_val;
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mesg->actual_length += t->len;
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if (bits <= 8) {
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const u8 *txbuf = t->tx_buf;
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u8 *rxbuf = t->rx_buf;
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while (i < t->len) {
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tx_val = txbuf ? txbuf[i] : 0;
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rx_val = atmel_spi_xchg(as, tx_val);
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if (rx_val < 0) {
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ret = rx_val;
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goto out;
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}
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if (rxbuf)
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rxbuf[i] = rx_val;
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i++;
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}
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} else if (bits <= 16) {
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const u16 *txbuf = t->tx_buf;
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u16 *rxbuf = t->rx_buf;
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while (i < t->len >> 1) {
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tx_val = txbuf ? txbuf[i] : 0;
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rx_val = atmel_spi_xchg(as, tx_val);
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if (rx_val < 0) {
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ret = rx_val;
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goto out;
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}
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if (rxbuf)
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rxbuf[i] = rx_val;
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i++;
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}
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}
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}
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out:
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atmel_spi_chipselect(spi, as, 0);
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return ret;
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}
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static int atmel_spi_probe(struct device_d *dev)
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{
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int ret = 0;
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struct spi_master *master;
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struct atmel_spi *as;
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struct at91_spi_platform_data *pdata = dev->platform_data;
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if (!pdata) {
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dev_err(dev, "missing platform data\n");
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return -EINVAL;
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}
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as = xzalloc(sizeof(*as));
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master = &as->master;
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master->dev = dev;
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as->clk = clk_get(dev, "spi_clk");
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if (IS_ERR(as->clk)) {
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dev_err(dev, "no spi_clk\n");
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ret = PTR_ERR(as->clk);
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goto out_free;
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}
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master->setup = atmel_spi_setup;
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master->transfer = atmel_spi_transfer;
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master->num_chipselect = pdata->num_chipselect;
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as->cs_pins = pdata->chipselect;
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as->regs = dev_request_mem_region(dev, 0);
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/* Initialize the hardware */
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clk_enable(as->clk);
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spi_writel(as, CR, SPI_BIT(SWRST));
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spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
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spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
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spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
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spi_writel(as, CR, SPI_BIT(SPIEN));
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dev_dbg(dev, "Atmel SPI Controller at initialized\n");
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ret = spi_register_master(master);
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if (ret)
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goto out_reset_hw;
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return 0;
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out_reset_hw:
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spi_writel(as, CR, SPI_BIT(SWRST));
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spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
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clk_disable(as->clk);
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clk_put(as->clk);
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out_free:
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free(as);
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return ret;
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}
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static struct driver_d atmel_spi_driver = {
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.name = "atmel_spi",
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.probe = atmel_spi_probe,
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};
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static int atmel_spi_init(void)
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{
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platform_driver_register(&atmel_spi_driver);
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return 0;
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}
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device_initcall(atmel_spi_init);
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