609 lines
14 KiB
C
609 lines
14 KiB
C
/*
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* Copyright (C) 2008 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <spi/spi.h>
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#include <xfuncs.h>
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#include <io.h>
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#include <errno.h>
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#include <malloc.h>
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#include <gpio.h>
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#include <mach/spi.h>
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#include <mach/generic.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#define CSPI_0_0_RXDATA 0x00
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#define CSPI_0_0_TXDATA 0x04
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#define CSPI_0_0_CTRL 0x08
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#define CSPI_0_0_INT 0x0C
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#define CSPI_0_0_DMA 0x18
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#define CSPI_0_0_STAT 0x0C
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#define CSPI_0_0_PERIOD 0x14
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#define CSPI_0_0_TEST 0x10
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#define CSPI_0_0_RESET 0x1C
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#define CSPI_0_0_CTRL_ENABLE (1 << 10)
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#define CSPI_0_0_CTRL_MASTER (1 << 11)
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#define CSPI_0_0_CTRL_XCH (1 << 9)
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#define CSPI_0_0_CTRL_LOWPOL (1 << 5)
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#define CSPI_0_0_CTRL_PHA (1 << 6)
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#define CSPI_0_0_CTRL_SSCTL (1 << 7)
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#define CSPI_0_0_CTRL_HIGHSSPOL (1 << 8)
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#define CSPI_0_0_CTRL_CS(x) (((x) & 0x3) << 19)
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#define CSPI_0_0_CTRL_BITCOUNT(x) (((x) & 0x1f) << 0)
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#define CSPI_0_0_CTRL_DATARATE(x) (((x) & 0x7) << 14)
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#define CSPI_0_0_CTRL_MAXDATRATE 0x10
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#define CSPI_0_0_CTRL_DATAMASK 0x1F
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#define CSPI_0_0_CTRL_DATASHIFT 14
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#define CSPI_0_0_STAT_TE (1 << 0)
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#define CSPI_0_0_STAT_TH (1 << 1)
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#define CSPI_0_0_STAT_TF (1 << 2)
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#define CSPI_0_0_STAT_RR (1 << 4)
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#define CSPI_0_0_STAT_RH (1 << 5)
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#define CSPI_0_0_STAT_RF (1 << 6)
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#define CSPI_0_0_STAT_RO (1 << 7)
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#define CSPI_0_0_PERIOD_32KHZ (1 << 15)
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#define CSPI_0_0_TEST_LBC (1 << 14)
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#define CSPI_0_7_RXDATA 0x00
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#define CSPI_0_7_TXDATA 0x04
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#define CSPI_0_7_CTRL 0x08
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#define CSPI_0_7_CTRL_ENABLE (1 << 0)
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#define CSPI_0_7_CTRL_MASTER (1 << 1)
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#define CSPI_0_7_CTRL_XCH (1 << 2)
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#define CSPI_0_7_CTRL_POL (1 << 4)
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#define CSPI_0_7_CTRL_PHA (1 << 5)
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#define CSPI_0_7_CTRL_SSCTL (1 << 6)
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#define CSPI_0_7_CTRL_SSPOL (1 << 7)
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#define CSPI_0_7_CTRL_CS_SHIFT 12
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#define CSPI_0_7_CTRL_DR_SHIFT 16
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#define CSPI_0_7_CTRL_BL_SHIFT 20
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#define CSPI_0_7_STAT 0x14
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#define CSPI_0_7_STAT_RR (1 << 3)
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#define CSPI_2_3_RXDATA 0x00
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#define CSPI_2_3_TXDATA 0x04
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#define CSPI_2_3_CTRL 0x08
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#define CSPI_2_3_CTRL_ENABLE (1 << 0)
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#define CSPI_2_3_CTRL_XCH (1 << 2)
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#define CSPI_2_3_CTRL_MODE(cs) (1 << ((cs) + 4))
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#define CSPI_2_3_CTRL_POSTDIV_OFFSET 8
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#define CSPI_2_3_CTRL_PREDIV_OFFSET 12
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#define CSPI_2_3_CTRL_CS(cs) ((cs) << 18)
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#define CSPI_2_3_CTRL_BL_OFFSET 20
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#define CSPI_2_3_CONFIG 0x0c
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#define CSPI_2_3_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
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#define CSPI_2_3_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
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#define CSPI_2_3_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
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#define CSPI_2_3_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
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#define CSPI_2_3_INT 0x10
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#define CSPI_2_3_INT_TEEN (1 << 0)
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#define CSPI_2_3_INT_RREN (1 << 3)
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#define CSPI_2_3_STAT 0x18
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#define CSPI_2_3_STAT_RR (1 << 3)
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enum imx_spi_devtype {
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#ifdef CONFIG_DRIVER_SPI_IMX1
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SPI_IMX_VER_IMX1,
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#endif
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#ifdef CONFIG_DRIVER_SPI_IMX_0_0
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SPI_IMX_VER_0_0,
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#endif
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#ifdef CONFIG_DRIVER_SPI_IMX_0_4
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SPI_IMX_VER_0_4,
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#endif
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#ifdef CONFIG_DRIVER_SPI_IMX_0_5
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SPI_IMX_VER_0_5,
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#endif
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#ifdef CONFIG_DRIVER_SPI_IMX_0_7
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SPI_IMX_VER_0_7,
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#endif
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#ifdef CONFIG_DRIVER_SPI_IMX_2_3
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SPI_IMX_VER_2_3,
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#endif
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};
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struct imx_spi {
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struct spi_master master;
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int *cs_array;
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void __iomem *regs;
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struct clk *clk;
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unsigned int (*xchg_single)(struct imx_spi *imx, u32 data);
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void (*chipselect)(struct spi_device *spi, int active);
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void (*init)(struct imx_spi *imx);
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};
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struct spi_imx_devtype_data {
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unsigned int (*xchg_single)(struct imx_spi *imx, u32 data);
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void (*chipselect)(struct spi_device *spi, int active);
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void (*init)(struct imx_spi *imx);
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};
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static int imx_spi_setup(struct spi_device *spi)
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{
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struct imx_spi *imx = container_of(spi->master, struct imx_spi, master);
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imx->chipselect(spi, 0);
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debug("%s mode 0x%08x bits_per_word: %d speed: %d\n",
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__FUNCTION__, spi->mode, spi->bits_per_word,
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spi->max_speed_hz);
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return 0;
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}
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#ifdef CONFIG_DRIVER_SPI_IMX_0_0
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static unsigned int cspi_0_0_xchg_single(struct imx_spi *imx, unsigned int data)
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{
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void __iomem *base = imx->regs;
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unsigned int cfg_reg = readl(base + CSPI_0_0_CTRL);
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writel(data, base + CSPI_0_0_TXDATA);
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cfg_reg |= CSPI_0_0_CTRL_XCH;
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writel(cfg_reg, base + CSPI_0_0_CTRL);
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while (!(readl(base + CSPI_0_0_INT) & CSPI_0_0_STAT_RR));
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return readl(base + CSPI_0_0_RXDATA);
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}
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static void cspi_0_0_chipselect(struct spi_device *spi, int is_active)
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{
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struct spi_master *master = spi->master;
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struct imx_spi *imx = container_of(master, struct imx_spi, master);
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void __iomem *base = imx->regs;
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unsigned int cs = 0;
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int gpio = imx->cs_array[spi->chip_select];
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u32 ctrl_reg;
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if (spi->mode & SPI_CS_HIGH)
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cs = 1;
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if (!is_active) {
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if (gpio >= 0)
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gpio_set_value(gpio, !cs);
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return;
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}
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ctrl_reg = CSPI_0_0_CTRL_BITCOUNT(spi->bits_per_word - 1)
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| CSPI_0_0_CTRL_DATARATE(7) /* FIXME: calculate data rate */
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| CSPI_0_0_CTRL_ENABLE
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| CSPI_0_0_CTRL_MASTER;
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if (gpio < 0) {
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ctrl_reg |= CSPI_0_0_CTRL_CS(gpio + 32);
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}
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if (spi->mode & SPI_CPHA)
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ctrl_reg |= CSPI_0_0_CTRL_PHA;
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if (spi->mode & SPI_CPOL)
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ctrl_reg |= CSPI_0_0_CTRL_LOWPOL;
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if (spi->mode & SPI_CS_HIGH)
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ctrl_reg |= CSPI_0_0_CTRL_HIGHSSPOL;
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writel(ctrl_reg, base + CSPI_0_0_CTRL);
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if (gpio >= 0)
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gpio_set_value(gpio, cs);
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}
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static void cspi_0_0_init(struct imx_spi *imx)
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{
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void __iomem *base = imx->regs;
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writel(CSPI_0_0_CTRL_ENABLE | CSPI_0_0_CTRL_MASTER,
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base + CSPI_0_0_CTRL);
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writel(CSPI_0_0_PERIOD_32KHZ,
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base + CSPI_0_0_PERIOD);
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while (readl(base + CSPI_0_0_INT) & CSPI_0_0_STAT_RR)
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readl(base + CSPI_0_0_RXDATA);
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writel(0, base + CSPI_0_0_INT);
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}
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#endif
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#ifdef CONFIG_DRIVER_SPI_IMX_0_7
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static unsigned int cspi_0_7_xchg_single(struct imx_spi *imx, unsigned int data)
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{
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void __iomem *base = imx->regs;
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unsigned int cfg_reg = readl(base + CSPI_0_7_CTRL);
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writel(data, base + CSPI_0_7_TXDATA);
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cfg_reg |= CSPI_0_7_CTRL_XCH;
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writel(cfg_reg, base + CSPI_0_7_CTRL);
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while (!(readl(base + CSPI_0_7_STAT) & CSPI_0_7_STAT_RR))
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;
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return readl(base + CSPI_0_7_RXDATA);
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}
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/* MX1, MX31, MX35, MX51 CSPI */
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static unsigned int spi_imx_clkdiv_2(unsigned int fin,
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unsigned int fspi)
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{
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int i, div = 4;
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for (i = 0; i < 7; i++) {
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if (fspi * div >= fin)
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return i;
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div <<= 1;
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}
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return 7;
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}
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static void cspi_0_7_chipselect(struct spi_device *spi, int is_active)
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{
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struct spi_master *master = spi->master;
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struct imx_spi *imx = container_of(master, struct imx_spi, master);
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void __iomem *base = imx->regs;
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unsigned int cs = 0;
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int gpio = imx->cs_array[spi->chip_select];
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unsigned int reg = CSPI_0_7_CTRL_ENABLE | CSPI_0_7_CTRL_MASTER;
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if (spi->mode & SPI_CS_HIGH)
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cs = 1;
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if (!is_active) {
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if (gpio >= 0)
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gpio_set_value(gpio, !cs);
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return;
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}
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reg |= spi_imx_clkdiv_2(clk_get_rate(imx->clk), spi->max_speed_hz) <<
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CSPI_0_7_CTRL_DR_SHIFT;
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reg |= (spi->bits_per_word - 1) << CSPI_0_7_CTRL_BL_SHIFT;
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reg |= CSPI_0_7_CTRL_SSCTL;
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if (spi->mode & SPI_CPHA)
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reg |= CSPI_0_7_CTRL_PHA;
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if (spi->mode & SPI_CPOL)
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reg |= CSPI_0_7_CTRL_POL;
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if (spi->mode & SPI_CS_HIGH)
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reg |= CSPI_0_7_CTRL_SSPOL;
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if (gpio < 0)
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reg |= (gpio + 32) << CSPI_0_7_CTRL_CS_SHIFT;
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writel(reg, base + CSPI_0_7_CTRL);
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if (gpio >= 0)
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gpio_set_value(gpio, cs);
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}
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static void cspi_0_7_init(struct imx_spi *imx)
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{
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void __iomem *base = imx->regs;
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/* drain receive buffer */
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while (readl(base + CSPI_0_7_STAT) & CSPI_0_7_STAT_RR)
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readl(base + CSPI_0_7_RXDATA);
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}
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#endif
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#ifdef CONFIG_DRIVER_SPI_IMX_2_3
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static unsigned int cspi_2_3_xchg_single(struct imx_spi *imx, unsigned int data)
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{
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void __iomem *base = imx->regs;
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unsigned int cfg_reg = readl(base + CSPI_2_3_CTRL);
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writel(data, base + CSPI_2_3_TXDATA);
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cfg_reg |= CSPI_2_3_CTRL_XCH;
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writel(cfg_reg, base + CSPI_2_3_CTRL);
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while (!(readl(base + CSPI_2_3_STAT) & CSPI_2_3_STAT_RR));
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return readl(base + CSPI_2_3_RXDATA);
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}
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static unsigned int cspi_2_3_clkdiv(unsigned int fin, unsigned int fspi)
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{
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/*
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* there are two 4-bit dividers, the pre-divider divides by
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* $pre, the post-divider by 2^$post
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*/
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unsigned int pre, post;
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if (unlikely(fspi > fin))
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return 0;
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post = fls(fin) - fls(fspi);
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if (fin > fspi << post)
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post++;
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/* now we have: (fin <= fspi << post) with post being minimal */
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post = max(4U, post) - 4;
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if (unlikely(post > 0xf)) {
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pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
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__func__, fspi, fin);
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return 0xff;
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}
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pre = DIV_ROUND_UP(fin, fspi << post) - 1;
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pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
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__func__, fin, fspi, post, pre);
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return (pre << CSPI_2_3_CTRL_PREDIV_OFFSET) |
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(post << CSPI_2_3_CTRL_POSTDIV_OFFSET);
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}
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static void cspi_2_3_chipselect(struct spi_device *spi, int is_active)
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{
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struct spi_master *master = spi->master;
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struct imx_spi *imx = container_of(master, struct imx_spi, master);
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void __iomem *base = imx->regs;
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unsigned int cs = spi->chip_select, gpio_cs = 0;
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int gpio = imx->cs_array[spi->chip_select];
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u32 ctrl, cfg = 0;
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if (spi->mode & SPI_CS_HIGH)
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gpio_cs = 1;
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if (!is_active) {
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if (gpio >= 0)
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gpio_direction_output(gpio, !gpio_cs);
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return;
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}
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ctrl = CSPI_2_3_CTRL_ENABLE;
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/* set master mode */
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ctrl |= CSPI_2_3_CTRL_MODE(cs);
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/* set clock speed */
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ctrl |= cspi_2_3_clkdiv(clk_get_rate(imx->clk), spi->max_speed_hz);
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/* set chip select to use */
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ctrl |= CSPI_2_3_CTRL_CS(cs);
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ctrl |= (spi->bits_per_word - 1) << CSPI_2_3_CTRL_BL_OFFSET;
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cfg |= CSPI_2_3_CONFIG_SBBCTRL(cs);
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if (spi->mode & SPI_CPHA)
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cfg |= CSPI_2_3_CONFIG_SCLKPHA(cs);
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if (spi->mode & SPI_CPOL)
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cfg |= CSPI_2_3_CONFIG_SCLKPOL(cs);
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if (spi->mode & SPI_CS_HIGH)
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cfg |= CSPI_2_3_CONFIG_SSBPOL(cs);
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writel(ctrl, base + CSPI_2_3_CTRL);
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writel(cfg, base + CSPI_2_3_CONFIG);
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if (gpio >= 0)
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gpio_set_value(gpio, gpio_cs);
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}
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static void cspi_2_3_init(struct imx_spi *imx)
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{
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}
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#endif
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static void imx_spi_do_transfer(struct spi_device *spi, struct spi_transfer *t)
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{
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struct imx_spi *imx = container_of(spi->master, struct imx_spi, master);
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unsigned i;
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if (spi->bits_per_word <= 8) {
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const u8 *tx_buf = t->tx_buf;
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u8 *rx_buf = t->rx_buf;
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u8 rx_val;
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for (i = 0; i < t->len; i++) {
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rx_val = imx->xchg_single(imx, tx_buf ? tx_buf[i] : 0);
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if (rx_buf)
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rx_buf[i] = rx_val;
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}
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} else if (spi->bits_per_word <= 16) {
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const u16 *tx_buf = t->tx_buf;
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u16 *rx_buf = t->rx_buf;
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u16 rx_val;
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for (i = 0; i < t->len >> 1; i++) {
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rx_val = imx->xchg_single(imx, tx_buf ? tx_buf[i] : 0);
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if (rx_buf)
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rx_buf[i] = rx_val;
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}
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} else if (spi->bits_per_word <= 32) {
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const u32 *tx_buf = t->tx_buf;
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u32 *rx_buf = t->rx_buf;
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u32 rx_val;
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for (i = 0; i < t->len >> 2; i++) {
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rx_val = imx->xchg_single(imx, tx_buf ? tx_buf[i] : 0);
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if (rx_buf)
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rx_buf[i] = rx_val;
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}
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}
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}
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static int imx_spi_transfer(struct spi_device *spi, struct spi_message *mesg)
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{
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struct imx_spi *imx = container_of(spi->master, struct imx_spi, master);
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struct spi_transfer *t = NULL;
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imx->chipselect(spi, 1);
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mesg->actual_length = 0;
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list_for_each_entry(t, &mesg->transfers, transfer_list) {
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imx_spi_do_transfer(spi, t);
|
|
mesg->actual_length += t->len;
|
|
}
|
|
|
|
imx->chipselect(spi, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct spi_imx_devtype_data spi_imx_devtype_data[] = {
|
|
#ifdef CONFIG_DRIVER_SPI_IMX_0_0
|
|
[SPI_IMX_VER_0_0] = {
|
|
.chipselect = cspi_0_0_chipselect,
|
|
.xchg_single = cspi_0_0_xchg_single,
|
|
.init = cspi_0_0_init,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_DRIVER_SPI_IMX_0_7
|
|
[SPI_IMX_VER_0_7] = {
|
|
.chipselect = cspi_0_7_chipselect,
|
|
.xchg_single = cspi_0_7_xchg_single,
|
|
.init = cspi_0_7_init,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_DRIVER_SPI_IMX_2_3
|
|
[SPI_IMX_VER_2_3] = {
|
|
.chipselect = cspi_2_3_chipselect,
|
|
.xchg_single = cspi_2_3_xchg_single,
|
|
.init = cspi_2_3_init,
|
|
},
|
|
#endif
|
|
};
|
|
|
|
static int imx_spi_dt_probe(struct imx_spi *imx)
|
|
{
|
|
struct device_node *node = imx->master.dev->device_node;
|
|
int ret, i;
|
|
u32 num_cs;
|
|
|
|
if (!node)
|
|
return -ENODEV;
|
|
|
|
ret = of_property_read_u32(node, "fsl,spi-num-chipselects", &num_cs);
|
|
if (ret)
|
|
return ret;
|
|
|
|
imx->master.num_chipselect = num_cs;
|
|
imx->cs_array = xzalloc(sizeof(u32) * num_cs);
|
|
|
|
for (i = 0; i < num_cs; i++) {
|
|
int cs_gpio = of_get_named_gpio(node, "cs-gpios", i);
|
|
imx->cs_array[i] = cs_gpio;
|
|
}
|
|
|
|
spi_of_register_slaves(&imx->master, node);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int imx_spi_probe(struct device_d *dev)
|
|
{
|
|
struct spi_master *master;
|
|
struct imx_spi *imx;
|
|
struct spi_imx_master *pdata = dev->platform_data;
|
|
enum imx_spi_devtype version;
|
|
int ret;
|
|
|
|
imx = xzalloc(sizeof(*imx));
|
|
|
|
master = &imx->master;
|
|
master->dev = dev;
|
|
|
|
master->setup = imx_spi_setup;
|
|
master->transfer = imx_spi_transfer;
|
|
|
|
if (pdata) {
|
|
master->num_chipselect = pdata->num_chipselect;
|
|
imx->cs_array = pdata->chipselect;
|
|
} else {
|
|
if (IS_ENABLED(CONFIG_OFDEVICE))
|
|
imx_spi_dt_probe(imx);
|
|
}
|
|
|
|
imx->clk = clk_get(dev, NULL);
|
|
if (IS_ERR(imx->clk)) {
|
|
ret = PTR_ERR(imx->clk);
|
|
goto err_free;
|
|
}
|
|
|
|
#ifdef CONFIG_DRIVER_SPI_IMX_0_0
|
|
if (cpu_is_mx27())
|
|
version = SPI_IMX_VER_0_0;
|
|
#endif
|
|
#ifdef CONFIG_DRIVER_SPI_IMX_0_7
|
|
if (cpu_is_mx25() || cpu_is_mx35())
|
|
version = SPI_IMX_VER_0_7;
|
|
#endif
|
|
#ifdef CONFIG_DRIVER_SPI_IMX_2_3
|
|
if (cpu_is_mx51() || cpu_is_mx53() || cpu_is_mx6())
|
|
version = SPI_IMX_VER_2_3;
|
|
#endif
|
|
imx->chipselect = spi_imx_devtype_data[version].chipselect;
|
|
imx->xchg_single = spi_imx_devtype_data[version].xchg_single;
|
|
imx->init = spi_imx_devtype_data[version].init;
|
|
imx->regs = dev_request_mem_region(dev, 0);
|
|
|
|
imx->init(imx);
|
|
|
|
spi_register_master(master);
|
|
|
|
return 0;
|
|
|
|
err_free:
|
|
free(imx);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static __maybe_unused struct of_device_id imx_spi_dt_ids[] = {
|
|
{
|
|
.compatible = "fsl,imx27-cspi",
|
|
}, {
|
|
.compatible = "fsl,imx35-cspi",
|
|
}, {
|
|
.compatible = "fsl,imx51-ecspi",
|
|
}, {
|
|
/* sentinel */
|
|
}
|
|
};
|
|
|
|
static struct driver_d imx_spi_driver = {
|
|
.name = "imx_spi",
|
|
.probe = imx_spi_probe,
|
|
.of_compatible = DRV_OF_COMPAT(imx_spi_dt_ids),
|
|
};
|
|
|
|
static int imx_spi_init(void)
|
|
{
|
|
platform_driver_register(&imx_spi_driver);
|
|
return 0;
|
|
}
|
|
|
|
device_initcall(imx_spi_init);
|
|
|