121 lines
3.3 KiB
C
121 lines
3.3 KiB
C
/*
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* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file
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* @brief Device driver for the Tegra 20 clock and reset (CAR) controller
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <mach/iomap.h>
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#include <mach/tegra20-car.h>
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static void __iomem *car_base;
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enum tegra20_clks {
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cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1,
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ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
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gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
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kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
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dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
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usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
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pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
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iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
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uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
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osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
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pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
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pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
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pll_x, audio, pll_ref, twd, clk_max,
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};
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static struct clk *clks[clk_max];
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static unsigned long get_osc_frequency(void)
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{
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u32 osc_ctrl = readl(car_base + CRC_OSC_CTRL);
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switch ((osc_ctrl & CRC_OSC_CTRL_OSC_FREQ_MASK) >>
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CRC_OSC_CTRL_OSC_FREQ_SHIFT) {
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case 0:
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return 13000000;
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case 1:
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return 19200000;
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case 2:
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return 12000000;
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case 3:
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return 26000000;
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default:
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return 0;
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}
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}
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static unsigned int get_pll_ref_div(void)
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{
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u32 osc_ctrl = readl(car_base + CRC_OSC_CTRL);
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return 1U << ((osc_ctrl & CRC_OSC_CTRL_PLL_REF_DIV_MASK) >>
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CRC_OSC_CTRL_PLL_REF_DIV_SHIFT);
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}
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static int tegra20_car_probe(struct device_d *dev)
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{
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car_base = dev_request_mem_region(dev, 0);
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if (!car_base)
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return -EBUSY;
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/* primary clocks */
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clks[clk_m] = clk_fixed("clk_m", get_osc_frequency());
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clks[clk_32k] = clk_fixed("clk_32k", 32768);
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clks[pll_ref] = clk_fixed_factor("pll_ref", "clk_m", 1,
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get_pll_ref_div());
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/* derived clocks */
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/* timer is a gate, but as it's enabled by BOOTROM we needn't worry */
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clks[timer] = clk_fixed_factor("timer", "clk_m", 1, 1);
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/* device to clock links */
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clkdev_add_physbase(clks[timer], TEGRA_TMR1_BASE, NULL);
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return 0;
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}
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static __maybe_unused struct of_device_id tegra20_car_dt_ids[] = {
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{
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.compatible = "nvidia,tegra20-car",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d tegra20_car_driver = {
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.probe = tegra20_car_probe,
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.name = "tegra20-car",
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.of_compatible = DRV_OF_COMPAT(tegra20_car_dt_ids),
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};
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static int tegra20_car_init(void)
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{
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return platform_driver_register(&tegra20_car_driver);
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}
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postcore_initcall(tegra20_car_init);
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