237 lines
6.5 KiB
C
237 lines
6.5 KiB
C
/*
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* On-Chip devices setup code for the AT91SAM9x5 family
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*
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* Copyright (C) 2010 Atmel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <common.h>
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#include <sizes.h>
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#include <asm/armlinux.h>
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#include <asm/hardware.h>
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#include <mach/board.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91sam9x5_matrix.h>
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#include <mach/gpio.h>
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#include <mach/io.h>
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#include <mach/cpu.h>
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#include "generic.h"
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void at91_add_device_sdram(u32 size)
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{
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arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
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add_mem_device("sram0", AT91SAM9X5_SRAM_BASE,
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AT91SAM9X5_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE);
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}
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/* --------------------------------------------------------------------
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* USB Host (OHCI)
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* -------------------------------------------------------------------- */
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#if defined(CONFIG_USB_OHCI)
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void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
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{
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int i;
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if (!data)
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return;
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/* Enable VBus control for UHP ports */
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for (i = 0; i < data->ports; i++) {
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if (data->vbus_pin[i])
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at91_set_gpio_output(data->vbus_pin[i], 0);
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}
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add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9X5_OHCI_BASE,
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SZ_1M, IORESOURCE_MEM, data);
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}
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#else
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void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
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#endif
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#if defined(CONFIG_DRIVER_NET_MACB)
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void at91_add_device_eth(int id, struct at91_ether_platform_data *data)
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{
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resource_size_t start;
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if (!data)
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return;
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if (cpu_is_at91sam9g15())
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return;
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if (id && !cpu_is_at91sam9x25())
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return;
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switch (id) {
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case 0:
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start = AT91SAM9X5_BASE_EMAC0;
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/* Pins used for MII and RMII */
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at91_set_A_periph(AT91_PIN_PB4, 0); /* ETXCK_EREFCK */
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at91_set_A_periph(AT91_PIN_PB3, 0); /* ERXDV */
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at91_set_A_periph(AT91_PIN_PB0, 0); /* ERX0 */
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at91_set_A_periph(AT91_PIN_PB1, 0); /* ERX1 */
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at91_set_A_periph(AT91_PIN_PB2, 0); /* ERXER */
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at91_set_A_periph(AT91_PIN_PB7, 0); /* ETXEN */
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at91_set_A_periph(AT91_PIN_PB9, 0); /* ETX0 */
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at91_set_A_periph(AT91_PIN_PB10, 0); /* ETX1 */
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at91_set_A_periph(AT91_PIN_PB5, 0); /* EMDIO */
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at91_set_A_periph(AT91_PIN_PB6, 0); /* EMDC */
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if (!(data->flags & AT91SAM_ETHER_RMII)) {
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at91_set_A_periph(AT91_PIN_PB16, 0); /* ECRS */
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at91_set_A_periph(AT91_PIN_PB17, 0); /* ECOL */
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at91_set_A_periph(AT91_PIN_PB13, 0); /* ERX2 */
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at91_set_A_periph(AT91_PIN_PB14, 0); /* ERX3 */
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at91_set_A_periph(AT91_PIN_PB15, 0); /* ERXCK */
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at91_set_A_periph(AT91_PIN_PB11, 0); /* ETX2 */
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at91_set_A_periph(AT91_PIN_PB12, 0); /* ETX3 */
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at91_set_A_periph(AT91_PIN_PB8, 0); /* ETXER */
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}
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break;
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case 1:
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start = AT91SAM9X5_BASE_EMAC1;
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if (!(data->flags & AT91SAM_ETHER_RMII))
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pr_warn("AT91: Only RMII available on interface macb%d.\n", id);
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/* Pins used for RMII */
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at91_set_B_periph(AT91_PIN_PC29, 0); /* ETXCK_EREFCK */
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at91_set_B_periph(AT91_PIN_PC28, 0); /* ECRSDV */
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at91_set_B_periph(AT91_PIN_PC20, 0); /* ERX0 */
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at91_set_B_periph(AT91_PIN_PC21, 0); /* ERX1 */
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at91_set_B_periph(AT91_PIN_PC16, 0); /* ERXER */
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at91_set_B_periph(AT91_PIN_PC27, 0); /* ETXEN */
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at91_set_B_periph(AT91_PIN_PC18, 0); /* ETX0 */
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at91_set_B_periph(AT91_PIN_PC19, 0); /* ETX1 */
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at91_set_B_periph(AT91_PIN_PC31, 0); /* EMDIO */
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at91_set_B_periph(AT91_PIN_PC30, 0); /* EMDC */
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break;
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default:
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return;
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}
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add_generic_device("macb", id, NULL, start, SZ_16K,
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IORESOURCE_MEM, data);
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}
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#else
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void at91_add_device_eth(int id, struct at91_ether_platform_data *data) {}
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#endif
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/* --------------------------------------------------------------------
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* NAND / SmartMedia
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* -------------------------------------------------------------------- */
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#if defined(CONFIG_NAND_ATMEL)
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static struct resource nand_resources[] = {
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[0] = {
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.start = AT91_CHIPSELECT_3,
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.end = AT91_CHIPSELECT_3 + SZ_256M - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AT91_BASE_SYS + AT91_PMECC,
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.end = AT91_BASE_SYS + AT91_PMECC + 512 - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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void __init at91_add_device_nand(struct atmel_nand_data *data)
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{
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unsigned long csa;
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if (!data)
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return;
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH);
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/* enable pin */
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if (data->enable_pin)
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at91_set_gpio_output(data->enable_pin, 1);
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/* ready/busy pin */
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if (data->rdy_pin)
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at91_set_gpio_input(data->rdy_pin, 1);
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/* card detect pin */
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if (data->det_pin)
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at91_set_gpio_input(data->det_pin, 1);
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add_generic_device_res("atmel_nand", 0, nand_resources,
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ARRAY_SIZE(nand_resources), data);
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}
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#else
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void __init at91_add_device_nand(struct atmel_nand_data *data) {}
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#endif
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/* --------------------------------------------------------------------
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* UART
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* -------------------------------------------------------------------- */
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#if defined(CONFIG_DRIVER_SERIAL_ATMEL)
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resource_size_t __init at91_configure_dbgu(void)
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{
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at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
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at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
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return AT91_BASE_SYS + AT91_DBGU;
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}
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resource_size_t __init at91_configure_usart0(unsigned pins)
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{
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at91_set_A_periph(AT91_PIN_PA0, 1); /* TXD0 */
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at91_set_A_periph(AT91_PIN_PA1, 0); /* RXD0 */
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if (pins & ATMEL_UART_RTS)
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at91_set_A_periph(AT91_PIN_PA2, 0); /* RTS0 */
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if (pins & ATMEL_UART_CTS)
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at91_set_A_periph(AT91_PIN_PA3, 0); /* CTS0 */
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return AT91SAM9X5_BASE_USART0;
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}
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resource_size_t __init at91_configure_usart1(unsigned pins)
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{
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at91_set_A_periph(AT91_PIN_PA5, 1); /* TXD1 */
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at91_set_A_periph(AT91_PIN_PA6, 0); /* RXD1 */
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if (pins & ATMEL_UART_RTS)
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at91_set_C_periph(AT91_PIN_PC27, 0); /* RTS1 */
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if (pins & ATMEL_UART_CTS)
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at91_set_C_periph(AT91_PIN_PC28, 0); /* CTS1 */
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return AT91SAM9X5_BASE_USART1;
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}
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resource_size_t __init at91_configure_usart2(unsigned pins)
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{
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at91_set_A_periph(AT91_PIN_PA7, 1); /* TXD2 */
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at91_set_A_periph(AT91_PIN_PA8, 0); /* RXD2 */
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if (pins & ATMEL_UART_RTS)
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at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS2 */
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if (pins & ATMEL_UART_CTS)
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at91_set_B_periph(AT91_PIN_PB1, 0); /* CTS2 */
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return AT91SAM9X5_BASE_USART2;
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}
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resource_size_t __init at91_configure_usart3(unsigned pins)
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{
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at91_set_B_periph(AT91_PIN_PC22, 1); /* TXD3 */
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at91_set_B_periph(AT91_PIN_PC23, 0); /* RXD3 */
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if (pins & ATMEL_UART_RTS)
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at91_set_B_periph(AT91_PIN_PC24, 0); /* RTS3 */
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if (pins & ATMEL_UART_CTS)
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at91_set_B_periph(AT91_PIN_PC25, 0); /* CTS3 */
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return AT91SAM9X5_BASE_USART3;
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}
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#endif
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