59 lines
1.9 KiB
C
59 lines
1.9 KiB
C
/*
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* Copyright (C) 2015 Pengutronix, Uwe Kleine-König <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/barebox-arm.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/io.h>
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#include <mach/lowlevel.h>
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#include <mach/common.h>
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extern char __dtb_armada_xp_rn2120_bb_start[];
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ENTRY_FUNCTION(start_netgear_rn2120, r0, r1, r2)
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{
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void *fdt;
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void __iomem *base = mvebu_get_initial_int_reg_base();
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arm_cpu_lowlevel_init();
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/*
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* This is necessary to allow the machine to draw more power. Probably
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* connected to a TI TPS65251. Without this resetting a phy makes the
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* SoC reset.
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* This is effectively gpio_direction_output(42, 1);
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*/
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writel((1 << 10) | readl(base + 0x18140), base + 0x18140);
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writel(~(1 << 10) & readl(base + 0x18144), base + 0x18144);
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/*
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* The vendor binary that initializes RAM doesn't program the SDRAM
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* Address Decoding registers to match the actual available RAM. But as
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* barebox later determines the RAM size from these, fix them up here.
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*/
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/* Win 1 Base Address Register: base=0x40000000 */
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writel(0x40000000, base + 0x20188);
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/* Win 1 Control Register: size=0x4000000, wincs=1, en=1*/
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writel(0x3fffffe5, base + 0x2018c);
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/* Win 0 Base Address Register is already 0, base=0x00000000 */
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/* Win 0 Control Register: size=0x4000000, wincs=0, en=1 */
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writel(0x3fffffe1, base + 0x20184);
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fdt = __dtb_armada_xp_rn2120_bb_start -
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get_runtime_offset();
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armada_370_xp_barebox_entry(fdt);
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}
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