239 lines
5.0 KiB
C
239 lines
5.0 KiB
C
/*
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* Copyright (C) 2014 Bo Shen <voice.shen@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <net.h>
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#include <init.h>
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#include <environment.h>
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#include <asm/armlinux.h>
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#include <generated/mach-types.h>
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
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#include <io.h>
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#include <mach/hardware.h>
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#include <nand.h>
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#include <sizes.h>
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#include <linux/mtd/nand.h>
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#include <mach/board.h>
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#include <mach/at91sam9_smc.h>
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#include <gpio.h>
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#include <mach/io.h>
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#include <mach/iomux.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91_rstc.h>
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#include <mach/at91sam9x5_matrix.h>
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#include <readkey.h>
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#include <poller.h>
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#include <linux/clk.h>
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#include <linux/phy.h>
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#include <linux/micrel_phy.h>
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#if defined(CONFIG_NAND_ATMEL)
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static struct atmel_nand_data nand_pdata = {
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.ale = 21,
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.cle = 22,
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.det_pin = -EINVAL,
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.rdy_pin = -EINVAL,
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.enable_pin = -EINVAL,
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.ecc_mode = NAND_ECC_HW,
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.pmecc_sector_size = 512,
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.pmecc_corr_cap = 4,
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#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
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.bus_width_16 = 1,
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#endif
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.on_flash_bbt = 1,
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};
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static struct sam9_smc_config sama5d3_xplained_nand_smc_config = {
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.ncs_read_setup = 0,
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.nrd_setup = 1,
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.ncs_write_setup = 0,
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.nwe_setup = 1,
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.ncs_read_pulse = 6,
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.nrd_pulse = 4,
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.ncs_write_pulse = 5,
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.nwe_pulse = 3,
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.read_cycle = 6,
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.write_cycle = 5,
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.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
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.tdf_cycles = 1,
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};
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static void ek_add_device_nand(void)
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{
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struct clk *clk = clk_get(NULL, "smc_clk");
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clk_enable(clk);
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/* setup bus-width (8 or 16) */
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if (nand_pdata.bus_width_16)
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sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_16;
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else
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sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_8;
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/* configure chip-select 3 (NAND) */
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sam9_smc_configure(0, 3, &sama5d3_xplained_nand_smc_config);
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at91_add_device_nand(&nand_pdata);
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}
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#else
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static void ek_add_device_nand(void) {}
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#endif
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#if defined(CONFIG_DRIVER_NET_MACB)
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static struct macb_platform_data gmac_pdata = {
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.phy_interface = PHY_INTERFACE_MODE_RGMII,
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.phy_addr = 7,
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};
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static struct macb_platform_data macb_pdata = {
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.phy_interface = PHY_INTERFACE_MODE_RMII,
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.phy_addr = 0,
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};
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static void ek_add_device_eth(void)
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{
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at91_add_device_eth(0, &gmac_pdata);
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at91_add_device_eth(1, &macb_pdata);
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}
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#else
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static void ek_add_device_eth(void) {}
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#endif
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#if defined(CONFIG_MCI_ATMEL)
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/*
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* MCI (SD/MMC)
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*/
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static struct atmel_mci_platform_data mci0_data = {
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.bus_width = 8,
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.detect_pin = AT91_PIN_PE0,
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.wp_pin = -EINVAL,
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};
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static void ek_add_device_mci(void)
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{
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/* MMC0 */
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at91_add_device_mci(0, &mci0_data);
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}
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#else
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static void ek_add_device_mci(void) {}
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#endif
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#ifdef CONFIG_LED_GPIO
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struct gpio_led leds[] = {
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{
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.gpio = AT91_PIN_PE23,
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.active_low = 1,
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.led = {
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.name = "d2",
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},
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}, {
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.gpio = AT91_PIN_PE24,
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.active_low = 1,
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.led = {
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.name = "d3",
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},
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},
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};
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static void ek_add_led(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(leds); i++) {
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at91_set_gpio_output(leds[i].gpio, leds[i].active_low);
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led_gpio_register(&leds[i]);
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}
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led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led);
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}
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#else
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static void ek_add_led(void) {}
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#endif
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static int sama5d3_xplained_mem_init(void)
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{
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at91_add_device_sdram(0);
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return 0;
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}
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mem_initcall(sama5d3_xplained_mem_init);
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static const struct devfs_partition sama5d3_xplained_nand0_partitions[] = {
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{
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.offset = 0x00000,
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.size = SZ_256K,
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.flags = DEVFS_PARTITION_FIXED,
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.name = "at91bootstrap_raw",
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.bbname = "at91bootstrap",
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}, {
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.offset = DEVFS_PARTITION_APPEND, /* 256 KiB */
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.size = SZ_256K + SZ_128K,
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.flags = DEVFS_PARTITION_FIXED,
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.name = "self_raw",
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.bbname = "self0",
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},
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/* hole of 128 KiB */
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{
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.offset = SZ_512K + SZ_256K,
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.size = SZ_256K,
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.flags = DEVFS_PARTITION_FIXED,
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.name = "env_raw",
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.bbname = "env0",
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}, {
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.offset = DEVFS_PARTITION_APPEND, /* 1 MiB */
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.size = SZ_256K,
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.flags = DEVFS_PARTITION_FIXED,
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.name = "env_raw1",
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.bbname = "env1",
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}, {
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/* sentinel */
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}
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};
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static int sama5d3_xplained_devices_init(void)
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{
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ek_add_device_nand();
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ek_add_led();
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ek_add_device_eth();
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ek_add_device_mci();
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devfs_create_partitions("nand0", sama5d3_xplained_nand0_partitions);
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return 0;
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}
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device_initcall(sama5d3_xplained_devices_init);
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static int sama5d3_xplained_console_init(void)
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{
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barebox_set_model("Atmel sama5d3_xplained");
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barebox_set_hostname("sama5d3_xplained");
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at91_register_uart(0, 0);
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return 0;
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}
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console_initcall(sama5d3_xplained_console_init);
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static int sama5d3_xplained_main_clock(void)
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{
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at91_set_main_clock(12000000);
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return 0;
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}
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pure_initcall(sama5d3_xplained_main_clock);
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