140 lines
3.5 KiB
C
140 lines
3.5 KiB
C
/*
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* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
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*
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* Based on the Linux Tegra clock code
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <io.h>
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#include <malloc.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include "clk.h"
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#define pll_out_enb(p) (BIT(p->enb_bit_idx))
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#define pll_out_rst(p) (BIT(p->rst_bit_idx))
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#define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw)
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static int clk_pll_out_is_enabled(struct clk *hw)
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{
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struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
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u32 val = readl(pll_out->reg);
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int state;
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state = (val & pll_out_enb(pll_out)) ? 1 : 0;
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if (!(val & (pll_out_rst(pll_out))))
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state = 0;
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return state;
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}
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static int clk_pll_out_enable(struct clk *hw)
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{
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struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
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u32 val;
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val = readl(pll_out->reg);
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val |= (pll_out_enb(pll_out) | pll_out_rst(pll_out));
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writel(val, pll_out->reg);
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udelay(2);
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return 0;
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}
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static void clk_pll_out_disable(struct clk *hw)
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{
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struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
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u32 val;
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val = readl(pll_out->reg);
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val &= ~(pll_out_enb(pll_out) | pll_out_rst(pll_out));
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writel(val, pll_out->reg);
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udelay(2);
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}
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static unsigned long clk_pll_out_recalc_rate(struct clk *hw,
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unsigned long parent_rate)
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{
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struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
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return pll_out->div->ops->recalc_rate(pll_out->div, parent_rate);
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}
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static long clk_pll_out_round_rate(struct clk *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
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return pll_out->div->ops->round_rate(pll_out->div, rate, prate);
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}
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static int clk_pll_out_set_rate(struct clk *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
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return pll_out->div->ops->set_rate(pll_out->div, rate, parent_rate);
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}
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const struct clk_ops tegra_clk_pll_out_ops = {
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.is_enabled = clk_pll_out_is_enabled,
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.enable = clk_pll_out_enable,
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.disable = clk_pll_out_disable,
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.recalc_rate = clk_pll_out_recalc_rate,
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.round_rate = clk_pll_out_round_rate,
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.set_rate = clk_pll_out_set_rate,
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};
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struct clk *tegra_clk_register_pll_out(const char *name,
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const char *parent_name, void __iomem *reg, u8 shift, u8 divider_flags)
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{
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struct tegra_clk_pll_out *pll_out;
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int ret;
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pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL);
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if (!pll_out)
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return NULL;
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pll_out->div = tegra_clk_divider_alloc(NULL, NULL, reg, 0, divider_flags, shift + 8, 8, 1);
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if (!pll_out->div) {
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kfree(pll_out);
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return NULL;
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}
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pll_out->parent = parent_name;
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pll_out->hw.name = name;
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pll_out->hw.ops = &tegra_clk_pll_out_ops;
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pll_out->hw.parent_names = (pll_out->parent ? &pll_out->parent : NULL);
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pll_out->hw.num_parents = (pll_out->parent ? 1 : 0);
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pll_out->reg = reg;
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pll_out->enb_bit_idx = shift + 1;
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pll_out->rst_bit_idx = shift;
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ret = clk_register(&pll_out->hw);
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if (ret) {
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tegra_clk_divider_free(pll_out->div);
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kfree(pll_out);
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return ERR_PTR(ret);
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}
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return &pll_out->hw;
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}
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