209 lines
5.3 KiB
C
209 lines
5.3 KiB
C
/*
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* Marvell EBU SoC common clock handling
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*
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* Based on Linux Marvell MVEBU clock providers
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* Copyright (C) 2012 Marvell
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <common.h>
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#include <init.h>
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#include <of.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include "common.h"
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/*
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* Core Clocks
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*/
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static struct clk_onecell_data clk_data;
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static struct of_device_id mvebu_coreclk_ids[] = {
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{ .compatible = "marvell,armada-370-core-clock",
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.data = (u32)&armada_370_coreclks },
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{ .compatible = "marvell,armada-xp-core-clock",
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.data = (u32)&armada_xp_coreclks },
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{ .compatible = "marvell,dove-core-clock",
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.data = (u32)&dove_coreclks },
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{ .compatible = "marvell,kirkwood-core-clock",
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.data = (u32)&kirkwood_coreclks },
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{ .compatible = "marvell,mv88f6180-core-clock",
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.data = (u32)&mv88f6180_coreclks },
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{ }
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};
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int mvebu_coreclk_probe(struct device_d *dev)
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{
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struct device_node *np = dev->device_node;
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const struct of_device_id *match;
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const struct coreclk_soc_desc *desc;
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const char *tclk_name = "tclk";
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const char *cpuclk_name = "cpuclk";
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void __iomem *base;
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unsigned long rate;
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int n;
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match = of_match_node(mvebu_coreclk_ids, np);
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if (!match)
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return -EINVAL;
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desc = (const struct coreclk_soc_desc *)match->data;
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/* Get SAR base address */
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base = dev_request_mem_region(dev, 0);
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if (!base)
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return -EINVAL;
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/* Allocate struct for TCLK, cpu clk, and core ratio clocks */
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clk_data.clk_num = 2 + desc->num_ratios;
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clk_data.clks = xzalloc(clk_data.clk_num * sizeof(struct clk *));
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/* Register TCLK */
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of_property_read_string_index(np, "clock-output-names", 0,
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&tclk_name);
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rate = desc->get_tclk_freq(base);
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clk_data.clks[0] = clk_fixed(tclk_name, rate);
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WARN_ON(IS_ERR(clk_data.clks[0]));
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/* Register CPU clock */
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of_property_read_string_index(np, "clock-output-names", 1,
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&cpuclk_name);
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rate = desc->get_cpu_freq(base);
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clk_data.clks[1] = clk_fixed(cpuclk_name, rate);
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WARN_ON(IS_ERR(clk_data.clks[1]));
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/* Register fixed-factor clocks derived from CPU clock */
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for (n = 0; n < desc->num_ratios; n++) {
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const char *rclk_name = desc->ratios[n].name;
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int mult, div;
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of_property_read_string_index(np, "clock-output-names",
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2+n, &rclk_name);
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desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
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clk_data.clks[2+n] = clk_fixed_factor(rclk_name, cpuclk_name,
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mult, div, 0);
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WARN_ON(IS_ERR(clk_data.clks[2+n]));
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};
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return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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}
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static struct driver_d mvebu_coreclk_driver = {
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.probe = mvebu_coreclk_probe,
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.name = "mvebu-core-clk",
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.of_compatible = DRV_OF_COMPAT(mvebu_coreclk_ids),
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};
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static int mvebu_coreclk_init(void)
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{
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return platform_driver_register(&mvebu_coreclk_driver);
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}
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core_initcall(mvebu_coreclk_init);
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/*
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* Clock Gating Control
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*/
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struct gate {
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struct clk *clk;
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int bit_idx;
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};
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struct clk_gating_ctrl {
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struct gate *gates;
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int num_gates;
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};
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static struct clk *clk_gating_get_src(
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struct of_phandle_args *clkspec, void *data)
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{
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struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data;
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int n;
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if (clkspec->args_count < 1)
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return ERR_PTR(-EINVAL);
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for (n = 0; n < ctrl->num_gates; n++) {
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if (clkspec->args[0] == ctrl->gates[n].bit_idx)
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return ctrl->gates[n].clk;
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}
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return ERR_PTR(-ENODEV);
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}
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static struct of_device_id mvebu_clk_gating_ids[] = {
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{ .compatible = "marvell,armada-370-gating-clock",
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.data = (u32)&armada_370_gating_desc },
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{ .compatible = "marvell,armada-xp-gating-clock",
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.data = (u32)&armada_xp_gating_desc },
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{ .compatible = "marvell,dove-gating-clock",
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.data = (u32)&dove_gating_desc },
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{ .compatible = "marvell,kirkwood-gating-clock",
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.data = (u32)&kirkwood_gating_desc },
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{ }
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};
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int mvebu_clk_gating_probe(struct device_d *dev)
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{
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struct device_node *np = dev->device_node;
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const struct of_device_id *match;
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const struct clk_gating_soc_desc *desc;
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struct clk_gating_ctrl *ctrl;
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struct gate *gate;
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struct clk *clk;
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void __iomem *base;
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const char *default_parent = NULL;
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int n;
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match = of_match_node(mvebu_clk_gating_ids, np);
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if (!match)
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return -EINVAL;
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desc = (const struct clk_gating_soc_desc *)match->data;
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base = dev_request_mem_region(dev, 0);
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if (!base)
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return -EINVAL;
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk))
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return -EINVAL;
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default_parent = clk->name;
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ctrl = xzalloc(sizeof(*ctrl));
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/* Count, allocate, and register clock gates */
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for (n = 0; desc[n].name;)
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n++;
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ctrl->num_gates = n;
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ctrl->gates = xzalloc(ctrl->num_gates * sizeof(*gate));
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for (n = 0, gate = ctrl->gates; n < ctrl->num_gates; n++, gate++) {
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const char *parent =
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(desc[n].parent) ? desc[n].parent : default_parent;
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gate->bit_idx = desc[n].bit_idx;
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gate->clk = clk_gate(desc[n].name, parent,
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base, desc[n].bit_idx, 0, 0);
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WARN_ON(IS_ERR(gate->clk));
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}
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return of_clk_add_provider(np, clk_gating_get_src, ctrl);
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}
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static struct driver_d mvebu_clk_gating_driver = {
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.probe = mvebu_clk_gating_probe,
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.name = "mvebu-clk-gating",
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.of_compatible = DRV_OF_COMPAT(mvebu_clk_gating_ids),
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};
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static int mvebu_clk_gating_init(void)
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{
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return platform_driver_register(&mvebu_clk_gating_driver);
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}
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postcore_initcall(mvebu_clk_gating_init);
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