118 lines
2.3 KiB
C
118 lines
2.3 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <common.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <io.h>
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#include "clk.h"
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#define SET 0x4
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#define CLR 0x8
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/**
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* struct clk_pll - mxs pll clock
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* @hw: clk_hw for the pll
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* @base: base address of the pll
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* @power: the shift of power bit
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* @rate: the clock rate of the pll
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*
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* The mxs pll is a fixed rate clock with power and gate control,
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* and the shift of gate bit is always 31.
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*/
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struct clk_pll {
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struct clk clk;
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const char *parent;
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void __iomem *base;
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u8 power;
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unsigned long rate;
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};
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#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, clk)
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static int clk_pll_enable(struct clk *clk)
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{
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struct clk_pll *pll = to_clk_pll(clk);
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writel(1 << pll->power, pll->base + SET);
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udelay(10);
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writel(1 << 31, pll->base + CLR);
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return 0;
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}
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static void clk_pll_disable(struct clk *clk)
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{
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struct clk_pll *pll = to_clk_pll(clk);
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writel(1 << 31, pll->base + SET);
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writel(1 << pll->power, pll->base + CLR);
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}
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static int clk_pll_is_enabled(struct clk *clk)
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{
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struct clk_pll *pll = to_clk_pll(clk);
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u32 val;
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val = readl(pll->base);
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if (val & (1 << 31))
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return 0;
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else
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return 1;
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}
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static unsigned long clk_pll_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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struct clk_pll *pll = to_clk_pll(clk);
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return pll->rate;
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}
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static const struct clk_ops clk_pll_ops = {
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.enable = clk_pll_enable,
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.disable = clk_pll_disable,
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.recalc_rate = clk_pll_recalc_rate,
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.is_enabled = clk_pll_is_enabled,
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};
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struct clk *mxs_clk_pll(const char *name, const char *parent_name,
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void __iomem *base, u8 power, unsigned long rate)
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{
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struct clk_pll *pll;
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int ret;
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pll = xzalloc(sizeof(*pll));
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if (!pll)
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return ERR_PTR(-ENOMEM);
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pll->parent = parent_name;
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pll->clk.name = name;
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pll->clk.ops = &clk_pll_ops;
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pll->clk.parent_names = &pll->parent;
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pll->clk.num_parents = 1;
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pll->base = base;
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pll->rate = rate;
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pll->power = power;
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ret = clk_register(&pll->clk);
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if (ret)
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ERR_PTR(ret);
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return &pll->clk;
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}
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