136 lines
2.8 KiB
C
136 lines
2.8 KiB
C
#include <common.h>
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#include <init.h>
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#include <asm/mmu.h>
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static unsigned long *ttb;
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void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
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unsigned int flags)
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{
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int i;
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phys >>= 20;
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virt >>= 20;
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for (i = size_m; i > 0; i--, virt++, phys++)
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ttb[virt] = (phys << 20) | flags;
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asm volatile (
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"mov r0, #0;"
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"mcr p15, 0, r0, c7, c6, 0;" /* flush d-cache */
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"mcr p15, 0, r0, c8, c7, 0;" /* flush i+d-TLBs */
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:
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:
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: "r0","memory" /* clobber list */
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);
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}
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/*
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* Prepare MMU for usage and create a flat mapping. Board
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* code is responsible to remap the SDRAM cached
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*/
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void mmu_init(void)
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{
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int i;
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ttb = xzalloc(0x8000);
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ttb = (void *)(((unsigned long)ttb + 0x4000) & ~0x3fff);
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/* Set the ttb register */
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asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb) /*:*/);
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/* Set the Domain Access Control Register */
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i = 0x3;
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asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
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/* create a flat mapping */
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arm_create_section(0, 0, 4096, PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT);
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}
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/*
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* enable the MMU. Should be called after mmu_init()
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*/
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void mmu_enable(void)
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{
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asm volatile (
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"mrc p15, 0, r1, c1, c0, 0;"
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"orr r1, r1, #0x0007;" /* enable MMU + Dcache */
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"mcr p15, 0, r1, c1, c0, 0"
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:
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:
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: "r1" /* Clobber list */
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);
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}
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/*
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* Clean and invalide caches, disable MMU
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*/
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void mmu_disable(void)
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{
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asm volatile (
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"nop; "
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"nop; "
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"nop; "
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"nop; "
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"nop; "
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"nop; "
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/* test, clean and invalidate cache */
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"1: mrc p15, 0, r15, c7, c14, 3;"
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" bne 1b;"
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" mov pc, lr;"
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" mov r0, #0x0;"
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" mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */
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" mcr p15, 0, r1, c7, c6, 0;" /* clear data cache */
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" mrc p15, 0, r1, c1, c0, 0;"
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" bic r1, r1, #0x0007;" /* disable MMU + DCache */
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" mcr p15, 0, r1, c1, c0, 0;"
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" mcr p15, 0, r0, c7, c6, 0;" /* flush d-cache */
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" mcr p15, 0, r0, c8, c7, 0;" /* flush i+d-TLBs */
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:
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:
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: "r0" /* Clobber list */
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);
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}
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/*
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* For boards which need coherent memory for DMA. The idea
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* is simple: Setup a uncached section containing your SDRAM
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* and call setup_dma_coherent() with the offset between the
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* cached and the uncached section. dma_alloc_coherent() then
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* works using normal malloc but returns the corresponding
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* pointer in the uncached area.
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*/
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static unsigned long dma_coherent_offset;
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void setup_dma_coherent(unsigned long offset)
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{
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dma_coherent_offset = offset;
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}
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void *dma_alloc_coherent(size_t size)
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{
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void *mem;
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mem = malloc(size);
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if (mem)
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return mem + dma_coherent_offset;
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return NULL;
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}
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unsigned long virt_to_phys(void *virt)
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{
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return (unsigned long)virt - dma_coherent_offset;
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}
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void *phys_to_virt(unsigned long phys)
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{
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return (void *)(phys + dma_coherent_offset);
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}
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void dma_free_coherent(void *mem)
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{
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free(mem - dma_coherent_offset);
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}
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