424 lines
8.9 KiB
C
424 lines
8.9 KiB
C
/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <net.h>
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#include <init.h>
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#include <environment.h>
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#include <mach/imx-regs.h>
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#include <fec.h>
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#include <notifier.h>
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#include <mach/gpio.h>
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#include <asm/armlinux.h>
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#include <generated/mach-types.h>
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#include <mach/pmic.h>
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
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#include <nand.h>
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#include <command.h>
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#include <spi/spi.h>
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#include <asm/io.h>
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#include <mach/imx-nand.h>
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#include <mach/imx-pll.h>
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#include <mach/imxfb.h>
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#include <asm/mmu.h>
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#include <usb/isp1504.h>
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#include <mach/spi.h>
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#include <mach/iomux-mx27.h>
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static struct device_d cfi_dev = {
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.name = "cfi_flash",
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.map_base = 0xC0000000,
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.size = 32 * 1024 * 1024,
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};
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static struct memory_platform_data ram_pdata = {
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.name = "ram0",
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.flags = DEVFS_RDWR,
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};
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static struct device_d sdram_dev = {
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.name = "mem",
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.map_base = 0xa0000000,
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.size = 128 * 1024 * 1024,
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.platform_data = &ram_pdata,
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};
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static struct memory_platform_data sram_pdata = {
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.name = "sram0",
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.flags = DEVFS_RDWR,
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};
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static struct device_d sram_dev = {
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.name = "mem",
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.map_base = 0xc8000000,
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.size = 512 * 1024, /* Can be up to 2MiB */
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.platform_data = &sram_pdata,
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};
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static struct fec_platform_data fec_info = {
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.xcv_type = MII100,
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.phy_addr = 1,
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};
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static struct device_d fec_dev = {
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.name = "fec_imx",
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.map_base = 0x1002b000,
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.platform_data = &fec_info,
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};
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static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
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static struct spi_imx_master pcm038_spi_0_data = {
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.chipselect = pcm038_spi_cs,
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.num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
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};
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static struct device_d spi_dev = {
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.name = "imx_spi",
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.map_base = 0x1000e000,
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.platform_data = &pcm038_spi_0_data,
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};
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static struct spi_board_info pcm038_spi_board_info[] = {
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{
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.name = "mc13783",
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.max_speed_hz = 3000000,
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.bus_num = 0,
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.chip_select = 0,
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}
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};
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static struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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.flash_bbt = 1,
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};
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static struct device_d nand_dev = {
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.name = "imx_nand",
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.map_base = 0xd8000000,
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.platform_data = &nand_info,
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};
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static struct imx_fb_videomode imxfb_mode = {
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.mode = {
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.name = "Sharp-LQ035Q7",
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.refresh = 60,
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.xres = 240,
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.yres = 320,
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.pixclock = 188679, /* in ps (5.3MHz) */
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.hsync_len = 7,
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.left_margin = 5,
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.right_margin = 16,
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.vsync_len = 1,
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.upper_margin = 7,
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.lower_margin = 9,
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},
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/*
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* - HSYNC active high
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* - VSYNC active high
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* - clk notenabled while idle
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* - clock not inverted
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* - data not inverted
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* - data enable low active
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* - enable sharp mode
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*/
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.pcr = 0xF00080C0,
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.bpp = 16,
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};
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static struct imx_fb_platform_data pcm038_fb_data = {
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.mode = &imxfb_mode,
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.pwmr = 0x00A903FF,
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.lscr1 = 0x00120300,
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.dmacr = 0x00020010,
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};
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static struct device_d imxfb_dev = {
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.name = "imxfb",
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.map_base = 0x10021000,
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.size = 0x1000,
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.platform_data = &pcm038_fb_data,
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};
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#ifdef CONFIG_USB
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static struct device_d usbh2_dev = {
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.name = "ehci",
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.map_base = IMX_OTG_BASE + 0x400,
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.size = 0x200,
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};
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static void pcm038_usbh_init(void)
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{
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uint32_t temp;
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temp = readl(IMX_OTG_BASE + 0x600);
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temp &= ~((3 << 21) | 1);
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temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20);
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writel(temp, IMX_OTG_BASE + 0x600);
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temp = readl(IMX_OTG_BASE + 0x584);
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temp &= ~(3 << 30);
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temp |= 2 << 30;
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writel(temp, IMX_OTG_BASE + 0x584);
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mdelay(10);
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isp1504_set_vbus_power((void *)(IMX_OTG_BASE + 0x570), 1);
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}
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#endif
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#ifdef CONFIG_MMU
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static void pcm038_mmu_init(void)
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{
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mmu_init();
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arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
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arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
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setup_dma_coherent(0x10000000);
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#if TEXT_BASE & (0x100000 - 1)
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#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
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#else
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arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED);
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#endif
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mmu_enable();
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}
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#else
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static void pcm038_mmu_init(void)
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{
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}
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#endif
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static int pcm038_devices_init(void)
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{
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int i;
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char *envdev;
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unsigned int mode[] = {
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PD0_AIN_FEC_TXD0,
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PD1_AIN_FEC_TXD1,
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PD2_AIN_FEC_TXD2,
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PD3_AIN_FEC_TXD3,
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PD4_AOUT_FEC_RX_ER,
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PD5_AOUT_FEC_RXD1,
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PD6_AOUT_FEC_RXD2,
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PD7_AOUT_FEC_RXD3,
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PD8_AF_FEC_MDIO,
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PD9_AIN_FEC_MDC | GPIO_PUEN,
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PD10_AOUT_FEC_CRS,
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PD11_AOUT_FEC_TX_CLK,
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PD12_AOUT_FEC_RXD0,
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PD13_AOUT_FEC_RX_DV,
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PD14_AOUT_FEC_RX_CLK,
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PD15_AOUT_FEC_COL,
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PD16_AIN_FEC_TX_ER,
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PF23_AIN_FEC_TX_EN,
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PE12_PF_UART1_TXD,
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PE13_PF_UART1_RXD,
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PE14_PF_UART1_CTS,
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PE15_PF_UART1_RTS,
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PD25_PF_CSPI1_RDY,
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GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT,
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PD29_PF_CSPI1_SCLK,
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PD30_PF_CSPI1_MISO,
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PD31_PF_CSPI1_MOSI,
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/* display */
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PA5_PF_LSCLK,
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PA6_PF_LD0,
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PA7_PF_LD1,
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PA8_PF_LD2,
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PA9_PF_LD3,
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PA10_PF_LD4,
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PA11_PF_LD5,
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PA12_PF_LD6,
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PA13_PF_LD7,
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PA14_PF_LD8,
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PA15_PF_LD9,
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PA16_PF_LD10,
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PA17_PF_LD11,
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PA18_PF_LD12,
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PA19_PF_LD13,
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PA20_PF_LD14,
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PA21_PF_LD15,
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PA22_PF_LD16,
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PA23_PF_LD17,
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PA24_PF_REV,
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PA25_PF_CLS,
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PA26_PF_PS,
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PA27_PF_SPL_SPR,
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PA28_PF_HSYNC,
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PA29_PF_VSYNC,
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PA30_PF_CONTRAST,
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PA31_PF_OE_ACD,
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/* USB host 2 */
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PA0_PF_USBH2_CLK,
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PA1_PF_USBH2_DIR,
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PA2_PF_USBH2_DATA7,
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PA3_PF_USBH2_NXT,
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PA4_PF_USBH2_STP,
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PD19_AF_USBH2_DATA4,
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PD20_AF_USBH2_DATA3,
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PD21_AF_USBH2_DATA6,
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PD22_AF_USBH2_DATA0,
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PD23_AF_USBH2_DATA2,
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PD24_AF_USBH2_DATA1,
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PD26_AF_USBH2_DATA5,
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};
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pcm038_mmu_init();
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/* configure 16 bit nor flash on cs0 */
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CS0U = 0x0000CC03;
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CS0L = 0xa0330D01;
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CS0A = 0x00220800;
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/* configure SRAM on cs1 */
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CS1U = 0x0000d843;
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CS1L = 0x22252521;
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CS1A = 0x22220a00;
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/* configure SJA1000 on cs4 */
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CS4U = 0x0000DCF6;
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CS4L = 0x444A0301;
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CS4A = 0x44443302;
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/* initizalize gpios */
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for (i = 0; i < ARRAY_SIZE(mode); i++)
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imx_gpio_mode(mode[i]);
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PCCR0 |= PCCR0_CSPI1_EN;
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PCCR1 |= PCCR1_PERCLK2_EN;
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gpio_direction_output(GPIO_PORTD | 28, 0);
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gpio_set_value(GPIO_PORTD | 28, 0);
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spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
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register_device(&spi_dev);
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register_device(&cfi_dev);
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register_device(&nand_dev);
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register_device(&sdram_dev);
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register_device(&sram_dev);
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register_device(&imxfb_dev);
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#ifdef CONFIG_USB
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pcm038_usbh_init();
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register_device(&usbh2_dev);
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#endif
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/* Register the fec device after the PLL re-initialisation
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* as the fec depends on the (now higher) ipg clock
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*/
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register_device(&fec_dev);
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switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
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case GPCR_BOOT_8BIT_NAND_2k:
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case GPCR_BOOT_16BIT_NAND_2k:
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case GPCR_BOOT_16BIT_NAND_512:
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case GPCR_BOOT_8BIT_NAND_512:
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devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
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dev_add_bb_dev("self_raw", "self0");
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devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
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dev_add_bb_dev("env_raw", "env0");
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envdev = "NAND";
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break;
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default:
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devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
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devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
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protect_file("/dev/env0", 1);
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envdev = "NOR";
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}
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printf("Using environment in %s Flash\n", envdev);
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armlinux_add_dram(&sdram_dev);
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armlinux_set_bootparams((void *)0xa0000100);
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armlinux_set_architecture(MACH_TYPE_PCM038);
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return 0;
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}
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device_initcall(pcm038_devices_init);
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static struct device_d pcm038_serial_device = {
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.name = "imx_serial",
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.map_base = IMX_UART1_BASE,
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.size = 4096,
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};
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static int pcm038_console_init(void)
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{
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/* bring PLLs to reset default */
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MPCTL0 = 0x00211803;
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SPCTL0 = 0x1002700c;
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CSCR = 0x33fc1307;
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register_device(&pcm038_serial_device);
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return 0;
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}
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console_initcall(pcm038_console_init);
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extern void *pcm038_pll_init, *pcm038_pll_init_end;
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static int pcm038_power_init(void)
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{
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int ret;
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void *vram = 0xffff4c00;
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void (*pllfunc)(void) = vram;
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printf("initialising PLLs: 0x%p 0x%p\n", &pcm038_pll_init);
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memcpy(vram, &pcm038_pll_init, 0x100);
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console_flush();
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ret = pmic_power();
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if (ret) {
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printf("Failed to initialize PMIC. Will continue with low CPU speed\n");
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return 0;
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}
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/* wait for good power level */
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udelay(100000);
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pllfunc();
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/* clock gating enable */
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GPCR = 0x00050f08;
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PCDR0 = 0x130410c3;
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PCDR1 = 0x09030911;
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/* Clocks have changed. Notify clients */
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clock_notifier_call_chain();
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return 0;
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}
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late_initcall(pcm038_power_init);
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