1250 lines
31 KiB
C
1250 lines
31 KiB
C
/*
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* Copyright (C) 2003 Rick Bronson
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*
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* Derived from drivers/mtd/nand/autcpu12.c
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* Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
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*
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* Derived from drivers/mtd/spia.c
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* Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
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*
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*
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* Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
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* Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
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*
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* Derived from Das U-Boot source code
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* (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
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* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <common.h>
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#include <driver.h>
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#include <malloc.h>
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#include <init.h>
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#include <gpio.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <io.h>
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#include <mach/board.h>
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#include <errno.h>
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/* Register access macros */
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#define ecc_readl(add, reg) \
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readl(add + ATMEL_ECC_##reg)
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#define ecc_writel(add, reg, value) \
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writel((value), add + ATMEL_ECC_##reg)
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#include "atmel_nand_ecc.h" /* Hardware ECC registers */
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/* oob layout for large page size
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* bad block info is on bytes 0 and 1
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* the bytes have to be consecutives to avoid
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* several NAND_CMD_RNDOUT during read
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*/
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static struct nand_ecclayout atmel_oobinfo_large = {
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.eccbytes = 4,
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.eccpos = {60, 61, 62, 63},
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.oobfree = {
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{2, 58}
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},
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};
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/* oob layout for small page size
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* bad block info is on bytes 4 and 5
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* the bytes have to be consecutives to avoid
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* several NAND_CMD_RNDOUT during read
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*/
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static struct nand_ecclayout atmel_oobinfo_small = {
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.eccbytes = 4,
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.eccpos = {0, 1, 2, 3},
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.oobfree = {
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{6, 10}
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},
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};
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struct atmel_nand_host {
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struct nand_chip nand_chip;
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struct mtd_info mtd;
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void __iomem *io_base;
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struct atmel_nand_data *board;
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struct device_d *dev;
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void __iomem *ecc;
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int pmecc_bytes_per_sector;
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int pmecc_sector_number;
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int pmecc_degree; /* Degree of remainders */
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int pmecc_cw_len; /* Length of codeword */
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void __iomem *pmerrloc_base;
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void __iomem *pmecc_rom_base;
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/* lookup table for alpha_to and index_of */
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void __iomem *pmecc_alpha_to;
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void __iomem *pmecc_index_of;
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/* data for pmecc computation */
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int16_t *pmecc_partial_syn;
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int16_t *pmecc_si;
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int16_t *pmecc_smu; /* Sigma table */
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int16_t *pmecc_lmu; /* polynomal order */
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int *pmecc_mu;
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int *pmecc_dmu;
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int *pmecc_delta;
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};
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static struct nand_ecclayout atmel_pmecc_oobinfo;
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/*
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* Enable NAND.
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*/
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static void atmel_nand_enable(struct atmel_nand_host *host)
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{
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if (host->board->enable_pin)
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gpio_set_value(host->board->enable_pin, 0);
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}
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/*
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* Disable NAND.
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*/
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static void atmel_nand_disable(struct atmel_nand_host *host)
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{
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if (host->board->enable_pin)
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gpio_set_value(host->board->enable_pin, 1);
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}
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/*
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* Hardware specific access to control-lines
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*/
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static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct atmel_nand_host *host = nand_chip->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_NCE)
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atmel_nand_enable(host);
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else
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atmel_nand_disable(host);
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}
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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writeb(cmd, host->io_base + (1 << host->board->cle));
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else
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writeb(cmd, host->io_base + (1 << host->board->ale));
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}
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/*
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* Read the Device Ready pin.
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*/
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static int atmel_nand_device_ready(struct mtd_info *mtd)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct atmel_nand_host *host = nand_chip->priv;
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return gpio_get_value(host->board->rdy_pin);
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}
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/*
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* Minimal-overhead PIO for data access.
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*/
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static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
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{
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struct nand_chip *nand_chip = mtd->priv;
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readsb(nand_chip->IO_ADDR_R, buf, len);
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}
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static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
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{
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struct nand_chip *nand_chip = mtd->priv;
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readsw(nand_chip->IO_ADDR_R, buf, len / 2);
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}
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static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
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{
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struct nand_chip *nand_chip = mtd->priv;
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writesb(nand_chip->IO_ADDR_W, buf, len);
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}
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static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
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{
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struct nand_chip *nand_chip = mtd->priv;
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writesw(nand_chip->IO_ADDR_W, buf, len / 2);
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}
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/*
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* Return number of ecc bytes per sector according to sector size and
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* correction capability
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*
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* Following table shows what at91 PMECC supported:
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* Correction Capability Sector_512_bytes Sector_1024_bytes
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* ===================== ================ =================
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* 2-bits 4-bytes 4-bytes
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* 4-bits 7-bytes 7-bytes
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* 8-bits 13-bytes 14-bytes
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* 12-bits 20-bytes 21-bytes
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* 24-bits 39-bytes 42-bytes
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*/
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static int pmecc_get_ecc_bytes(int cap, int sector_size)
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{
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int m = 12 + sector_size / 512;
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return (m * cap + 7) / 8;
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}
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static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
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int oobsize, int ecc_len)
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{
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int i;
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layout->eccbytes = ecc_len;
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/* ECC will occupy the last ecc_len bytes continuously */
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for (i = 0; i < ecc_len; i++)
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layout->eccpos[i] = oobsize - ecc_len + i;
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layout->oobfree[0].offset = 2;
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layout->oobfree[0].length =
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oobsize - ecc_len - layout->oobfree[0].offset;
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}
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static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
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{
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int table_size;
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table_size = host->board->pmecc_sector_size == 512 ?
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PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
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return host->pmecc_rom_base + host->board->pmecc_lookup_table_offset +
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table_size * sizeof(int16_t);
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}
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static void pmecc_data_free(struct atmel_nand_host *host)
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{
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kfree(host->pmecc_partial_syn);
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kfree(host->pmecc_si);
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kfree(host->pmecc_lmu);
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kfree(host->pmecc_smu);
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kfree(host->pmecc_mu);
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kfree(host->pmecc_dmu);
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kfree(host->pmecc_delta);
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}
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static int pmecc_data_alloc(struct atmel_nand_host *host)
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{
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const int cap = host->board->pmecc_corr_cap;
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host->pmecc_partial_syn = kzalloc((2 * cap + 1) * sizeof(int16_t),
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GFP_KERNEL);
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host->pmecc_si = kzalloc((2 * cap + 1) * sizeof(int16_t), GFP_KERNEL);
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host->pmecc_lmu = kzalloc((cap + 1) * sizeof(int16_t), GFP_KERNEL);
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host->pmecc_smu = kzalloc((cap + 2) * (2 * cap + 1) * sizeof(int16_t),
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GFP_KERNEL);
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host->pmecc_mu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
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host->pmecc_dmu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
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host->pmecc_delta = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL);
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if (host->pmecc_partial_syn &&
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host->pmecc_si &&
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host->pmecc_lmu &&
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host->pmecc_smu &&
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host->pmecc_mu &&
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host->pmecc_dmu &&
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host->pmecc_delta)
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return 0;
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/* error happened */
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pmecc_data_free(host);
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return -ENOMEM;
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}
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static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct atmel_nand_host *host = nand_chip->priv;
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int i;
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uint32_t value;
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/* Fill odd syndromes */
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for (i = 0; i < host->board->pmecc_corr_cap; i++) {
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value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
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if (i & 1)
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value >>= 16;
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value &= 0xffff;
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host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
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}
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}
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static void pmecc_substitute(struct mtd_info *mtd)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct atmel_nand_host *host = nand_chip->priv;
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int16_t __iomem *alpha_to = host->pmecc_alpha_to;
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int16_t __iomem *index_of = host->pmecc_index_of;
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int16_t *partial_syn = host->pmecc_partial_syn;
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const int cap = host->board->pmecc_corr_cap;
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int16_t *si;
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int i, j;
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/* si[] is a table that holds the current syndrome value,
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* an element of that table belongs to the field
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*/
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si = host->pmecc_si;
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memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
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/* Computation 2t syndromes based on S(x) */
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/* Odd syndromes */
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for (i = 1; i < 2 * cap; i += 2) {
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for (j = 0; j < host->pmecc_degree; j++) {
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if (partial_syn[i] & ((unsigned short)0x1 << j))
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si[i] = readw(alpha_to + i * j) ^ si[i];
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}
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}
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/* Even syndrome = (Odd syndrome) ** 2 */
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for (i = 2, j = 1; j <= cap; i = ++j << 1) {
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if (si[j] == 0) {
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si[i] = 0;
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} else {
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int16_t tmp;
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tmp = readw(index_of + si[j]);
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tmp = (tmp * 2) % host->pmecc_cw_len;
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si[i] = readw(alpha_to + tmp);
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}
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}
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return;
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}
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static void pmecc_get_sigma(struct mtd_info *mtd)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct atmel_nand_host *host = nand_chip->priv;
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int16_t *lmu = host->pmecc_lmu;
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int16_t *si = host->pmecc_si;
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int *mu = host->pmecc_mu;
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int *dmu = host->pmecc_dmu; /* Discrepancy */
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int *delta = host->pmecc_delta; /* Delta order */
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int cw_len = host->pmecc_cw_len;
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const int16_t cap = host->board->pmecc_corr_cap;
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const int num = 2 * cap + 1;
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int16_t __iomem *index_of = host->pmecc_index_of;
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int16_t __iomem *alpha_to = host->pmecc_alpha_to;
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int i, j, k;
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uint32_t dmu_0_count, tmp;
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int16_t *smu = host->pmecc_smu;
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/* index of largest delta */
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int ro;
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int largest;
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int diff;
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dmu_0_count = 0;
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/* First Row */
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/* Mu */
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mu[0] = -1;
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memset(smu, 0, sizeof(int16_t) * num);
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smu[0] = 1;
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/* discrepancy set to 1 */
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dmu[0] = 1;
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/* polynom order set to 0 */
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lmu[0] = 0;
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delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
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/* Second Row */
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/* Mu */
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mu[1] = 0;
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/* Sigma(x) set to 1 */
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memset(&smu[num], 0, sizeof(int16_t) * num);
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smu[num] = 1;
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/* discrepancy set to S1 */
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dmu[1] = si[1];
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/* polynom order set to 0 */
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lmu[1] = 0;
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delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
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/* Init the Sigma(x) last row */
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memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
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for (i = 1; i <= cap; i++) {
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mu[i + 1] = i << 1;
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/* Begin Computing Sigma (Mu+1) and L(mu) */
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/* check if discrepancy is set to 0 */
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if (dmu[i] == 0) {
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dmu_0_count++;
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tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
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if ((cap - (lmu[i] >> 1) - 1) & 0x1)
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tmp += 2;
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else
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tmp += 1;
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if (dmu_0_count == tmp) {
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for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
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smu[(cap + 1) * num + j] =
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smu[i * num + j];
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lmu[cap + 1] = lmu[i];
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return;
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}
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/* copy polynom */
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for (j = 0; j <= lmu[i] >> 1; j++)
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smu[(i + 1) * num + j] = smu[i * num + j];
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/* copy previous polynom order to the next */
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lmu[i + 1] = lmu[i];
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} else {
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ro = 0;
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largest = -1;
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/* find largest delta with dmu != 0 */
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for (j = 0; j < i; j++) {
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if ((dmu[j]) && (delta[j] > largest)) {
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largest = delta[j];
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ro = j;
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}
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}
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/* compute difference */
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diff = (mu[i] - mu[ro]);
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/* Compute degree of the new smu polynomial */
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if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
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lmu[i + 1] = lmu[i];
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else
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lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
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/* Init smu[i+1] with 0 */
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for (k = 0; k < num; k++)
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smu[(i + 1) * num + k] = 0;
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/* Compute smu[i+1] */
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for (k = 0; k <= lmu[ro] >> 1; k++) {
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int16_t a, b, c;
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if (!(smu[ro * num + k] && dmu[i]))
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continue;
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a = readw(index_of + dmu[i]);
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b = readw(index_of + dmu[ro]);
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c = readw(index_of + smu[ro * num + k]);
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tmp = a + (cw_len - b) + c;
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a = readw(alpha_to + tmp % cw_len);
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smu[(i + 1) * num + (k + diff)] = a;
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}
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for (k = 0; k <= lmu[i] >> 1; k++)
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smu[(i + 1) * num + k] ^= smu[i * num + k];
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}
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/* End Computing Sigma (Mu+1) and L(mu) */
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/* In either case compute delta */
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delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
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/* Do not compute discrepancy for the last iteration */
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if (i >= cap)
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continue;
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for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
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tmp = 2 * (i - 1);
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if (k == 0) {
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dmu[i + 1] = si[tmp + 3];
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} else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
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int16_t a, b, c;
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a = readw(index_of +
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smu[(i + 1) * num + k]);
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b = si[2 * (i - 1) + 3 - k];
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c = readw(index_of + b);
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tmp = a + c;
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tmp %= cw_len;
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dmu[i + 1] = readw(alpha_to + tmp) ^
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dmu[i + 1];
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}
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}
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}
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return;
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}
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static int pmecc_err_location(struct mtd_info *mtd)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct atmel_nand_host *host = nand_chip->priv;
|
|
const int cap = host->board->pmecc_corr_cap;
|
|
const int num = 2 * cap + 1;
|
|
int sector_size = host->board->pmecc_sector_size;
|
|
int err_nbr = 0; /* number of error */
|
|
int roots_nbr; /* number of roots */
|
|
int i, ret;
|
|
uint32_t val;
|
|
int16_t *smu = host->pmecc_smu;
|
|
|
|
pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
|
|
|
|
for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
|
|
pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
|
|
smu[(cap + 1) * num + i]);
|
|
err_nbr++;
|
|
}
|
|
|
|
val = (err_nbr - 1) << 16;
|
|
if (sector_size == 1024)
|
|
val |= 1;
|
|
|
|
pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
|
|
pmerrloc_writel(host->pmerrloc_base, ELEN,
|
|
sector_size * 8 + host->pmecc_degree * cap);
|
|
|
|
ret = wait_on_timeout(PMECC_MAX_TIMEOUT_MS,
|
|
pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
|
|
& PMERRLOC_CALC_DONE);
|
|
if (ret) {
|
|
dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
|
|
& PMERRLOC_ERR_NUM_MASK) >> 8;
|
|
/* Number of roots == degree of smu hence <= cap */
|
|
if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
|
|
return err_nbr - 1;
|
|
|
|
/* Number of roots does not match the degree of smu
|
|
* unable to correct error */
|
|
return -1;
|
|
}
|
|
|
|
static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
|
|
int sector_num, int extra_bytes, int err_nbr)
|
|
{
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
struct atmel_nand_host *host = nand_chip->priv;
|
|
int i = 0;
|
|
int byte_pos, bit_pos, sector_size, pos;
|
|
uint32_t tmp;
|
|
uint8_t err_byte;
|
|
|
|
sector_size = host->board->pmecc_sector_size;
|
|
|
|
while (err_nbr) {
|
|
tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
|
|
byte_pos = tmp / 8;
|
|
bit_pos = tmp % 8;
|
|
|
|
if (byte_pos >= (sector_size + extra_bytes))
|
|
BUG(); /* should never happen */
|
|
|
|
if (byte_pos < sector_size) {
|
|
err_byte = *(buf + byte_pos);
|
|
*(buf + byte_pos) ^= (1 << bit_pos);
|
|
|
|
pos = sector_num * host->board->pmecc_sector_size + byte_pos;
|
|
dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
|
|
pos, bit_pos, err_byte, *(buf + byte_pos));
|
|
} else {
|
|
/* Bit flip in OOB area */
|
|
tmp = sector_num * host->pmecc_bytes_per_sector
|
|
+ (byte_pos - sector_size);
|
|
err_byte = ecc[tmp];
|
|
ecc[tmp] ^= (1 << bit_pos);
|
|
|
|
pos = tmp + nand_chip->ecc.layout->eccpos[0];
|
|
dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
|
|
pos, bit_pos, err_byte, ecc[tmp]);
|
|
}
|
|
|
|
i++;
|
|
err_nbr--;
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
|
|
u8 *ecc)
|
|
{
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
struct atmel_nand_host *host = nand_chip->priv;
|
|
int i, err_nbr, eccbytes;
|
|
uint8_t *buf_pos;
|
|
|
|
eccbytes = nand_chip->ecc.bytes;
|
|
for (i = 0; i < eccbytes; i++)
|
|
if (ecc[i] != 0xff)
|
|
goto normal_check;
|
|
/* Erased page, return OK */
|
|
return 0;
|
|
|
|
normal_check:
|
|
for (i = 0; i < host->pmecc_sector_number; i++) {
|
|
err_nbr = 0;
|
|
if (pmecc_stat & 0x1) {
|
|
buf_pos = buf + i * host->board->pmecc_sector_size;
|
|
|
|
pmecc_gen_syndrome(mtd, i);
|
|
pmecc_substitute(mtd);
|
|
pmecc_get_sigma(mtd);
|
|
|
|
err_nbr = pmecc_err_location(mtd);
|
|
if (err_nbr == -1) {
|
|
dev_err(host->dev, "PMECC: Too many errors\n");
|
|
mtd->ecc_stats.failed++;
|
|
return -EIO;
|
|
} else {
|
|
pmecc_correct_data(mtd, buf_pos, ecc, i,
|
|
host->pmecc_bytes_per_sector, err_nbr);
|
|
mtd->ecc_stats.corrected += err_nbr;
|
|
}
|
|
}
|
|
pmecc_stat >>= 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
|
|
struct nand_chip *chip, uint8_t *buf)
|
|
{
|
|
struct atmel_nand_host *host = chip->priv;
|
|
int eccsize = chip->ecc.size;
|
|
uint8_t *oob = chip->oob_poi;
|
|
uint32_t *eccpos = chip->ecc.layout->eccpos;
|
|
uint32_t stat;
|
|
int ret;
|
|
|
|
pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
|
|
pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
|
|
pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG)
|
|
& ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
|
|
|
|
pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
|
|
pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
|
|
|
|
chip->read_buf(mtd, buf, eccsize);
|
|
chip->read_buf(mtd, oob, mtd->oobsize);
|
|
|
|
ret = wait_on_timeout(PMECC_MAX_TIMEOUT_MS,
|
|
!(pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY));
|
|
if (ret) {
|
|
dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
stat = pmecc_readl_relaxed(host->ecc, ISR);
|
|
if (stat != 0)
|
|
if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
|
|
return -EIO;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void atmel_nand_pmecc_write_page(struct mtd_info *mtd,
|
|
struct nand_chip *chip, const uint8_t *buf)
|
|
{
|
|
struct atmel_nand_host *host = chip->priv;
|
|
uint32_t *eccpos = chip->ecc.layout->eccpos;
|
|
int i, j, ret;
|
|
|
|
pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
|
|
pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
|
|
|
|
pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) |
|
|
PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
|
|
|
|
pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
|
|
pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
|
|
|
|
chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
|
|
|
|
ret = wait_on_timeout(PMECC_MAX_TIMEOUT_MS,
|
|
!(pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY));
|
|
if (ret) {
|
|
dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
|
|
return;
|
|
}
|
|
|
|
for (i = 0; i < host->pmecc_sector_number; i++) {
|
|
for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
|
|
int pos;
|
|
|
|
pos = i * host->pmecc_bytes_per_sector + j;
|
|
chip->oob_poi[eccpos[pos]] =
|
|
pmecc_readb_ecc_relaxed(host->ecc, i, j);
|
|
}
|
|
}
|
|
chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
}
|
|
|
|
static void atmel_pmecc_core_init(struct mtd_info *mtd)
|
|
{
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
struct atmel_nand_host *host = nand_chip->priv;
|
|
uint32_t val = 0;
|
|
struct nand_ecclayout *ecc_layout;
|
|
|
|
pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
|
|
pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
|
|
|
|
switch (host->board->pmecc_corr_cap) {
|
|
case 2:
|
|
val = PMECC_CFG_BCH_ERR2;
|
|
break;
|
|
case 4:
|
|
val = PMECC_CFG_BCH_ERR4;
|
|
break;
|
|
case 8:
|
|
val = PMECC_CFG_BCH_ERR8;
|
|
break;
|
|
case 12:
|
|
val = PMECC_CFG_BCH_ERR12;
|
|
break;
|
|
case 24:
|
|
val = PMECC_CFG_BCH_ERR24;
|
|
break;
|
|
}
|
|
|
|
if (host->board->pmecc_sector_size == 512)
|
|
val |= PMECC_CFG_SECTOR512;
|
|
else if (host->board->pmecc_sector_size == 1024)
|
|
val |= PMECC_CFG_SECTOR1024;
|
|
|
|
switch (host->pmecc_sector_number) {
|
|
case 1:
|
|
val |= PMECC_CFG_PAGE_1SECTOR;
|
|
break;
|
|
case 2:
|
|
val |= PMECC_CFG_PAGE_2SECTORS;
|
|
break;
|
|
case 4:
|
|
val |= PMECC_CFG_PAGE_4SECTORS;
|
|
break;
|
|
case 8:
|
|
val |= PMECC_CFG_PAGE_8SECTORS;
|
|
break;
|
|
}
|
|
|
|
val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
|
|
| PMECC_CFG_AUTO_DISABLE);
|
|
pmecc_writel(host->ecc, CFG, val);
|
|
|
|
ecc_layout = nand_chip->ecc.layout;
|
|
pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
|
|
pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
|
|
pmecc_writel(host->ecc, EADDR,
|
|
ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
|
|
/* See datasheet about PMECC Clock Control Register */
|
|
pmecc_writel(host->ecc, CLK, 2);
|
|
pmecc_writel(host->ecc, IDR, 0xff);
|
|
pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
|
|
}
|
|
|
|
static int __init atmel_pmecc_nand_init_params(struct device_d *dev,
|
|
struct atmel_nand_host *host)
|
|
{
|
|
struct mtd_info *mtd = &host->mtd;
|
|
struct nand_chip *nand_chip = &host->nand_chip;
|
|
int cap, sector_size, err_no;
|
|
|
|
cap = host->board->pmecc_corr_cap;
|
|
sector_size = host->board->pmecc_sector_size;
|
|
dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
|
|
cap, sector_size);
|
|
|
|
host->ecc = dev_request_mem_region(dev, 1);
|
|
if (host->ecc == NULL) {
|
|
dev_err(host->dev, "ioremap failed\n");
|
|
return -EIO;
|
|
}
|
|
|
|
host->pmerrloc_base = dev_request_mem_region(dev, 2);
|
|
host->pmecc_rom_base = dev_request_mem_region(dev, 3);
|
|
|
|
if (!host->pmerrloc_base || !host->pmecc_rom_base) {
|
|
dev_err(host->dev,
|
|
"Can not get I/O resource for PMECC ERRLOC controller or ROM!\n");
|
|
return -EIO;
|
|
}
|
|
|
|
/* ECC is calculated for the whole page (1 step) */
|
|
nand_chip->ecc.size = mtd->writesize;
|
|
|
|
/* set ECC page size and oob layout */
|
|
switch (mtd->writesize) {
|
|
case 2048:
|
|
case 4096:
|
|
host->pmecc_degree = PMECC_GF_DIMENSION_13;
|
|
host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
|
|
host->pmecc_sector_number = mtd->writesize / sector_size;
|
|
host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
|
|
cap, sector_size);
|
|
host->pmecc_alpha_to = pmecc_get_alpha_to(host);
|
|
host->pmecc_index_of = host->pmecc_rom_base +
|
|
host->board->pmecc_lookup_table_offset;
|
|
|
|
nand_chip->ecc.steps = 1;
|
|
nand_chip->ecc.bytes = host->pmecc_bytes_per_sector *
|
|
host->pmecc_sector_number;
|
|
if (nand_chip->ecc.bytes > mtd->oobsize - 2) {
|
|
dev_err(host->dev, "No room for ECC bytes\n");
|
|
return -EINVAL;
|
|
}
|
|
pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
|
|
mtd->oobsize,
|
|
nand_chip->ecc.bytes);
|
|
nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
|
|
break;
|
|
case 512:
|
|
case 1024:
|
|
/* TODO */
|
|
dev_warn(host->dev,
|
|
"Unsupported page size for PMECC, use Software ECC\n");
|
|
default:
|
|
/* page size not handled by HW ECC */
|
|
/* switching back to soft ECC */
|
|
nand_chip->ecc.mode = NAND_ECC_SOFT;
|
|
return 0;
|
|
}
|
|
|
|
/* Allocate data for PMECC computation */
|
|
err_no = pmecc_data_alloc(host);
|
|
if (err_no) {
|
|
dev_err(host->dev,
|
|
"Cannot allocate memory for PMECC computation!\n");
|
|
return err_no;
|
|
}
|
|
|
|
nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
|
|
nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
|
|
|
|
atmel_pmecc_core_init(mtd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Calculate HW ECC
|
|
*
|
|
* function called after a write
|
|
*
|
|
* mtd: MTD block structure
|
|
* dat: raw data (unused)
|
|
* ecc_code: buffer for ECC
|
|
*/
|
|
static int atmel_nand_calculate(struct mtd_info *mtd,
|
|
const u_char *dat, unsigned char *ecc_code)
|
|
{
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
struct atmel_nand_host *host = nand_chip->priv;
|
|
unsigned int ecc_value;
|
|
|
|
/* get the first 2 ECC bytes */
|
|
ecc_value = ecc_readl(host->ecc, PR);
|
|
|
|
ecc_code[0] = ecc_value & 0xFF;
|
|
ecc_code[1] = (ecc_value >> 8) & 0xFF;
|
|
|
|
/* get the last 2 ECC bytes */
|
|
ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
|
|
|
|
ecc_code[2] = ecc_value & 0xFF;
|
|
ecc_code[3] = (ecc_value >> 8) & 0xFF;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* HW ECC read page function
|
|
*
|
|
* mtd: mtd info structure
|
|
* chip: nand chip info structure
|
|
* buf: buffer to store read data
|
|
*/
|
|
static int atmel_nand_read_page(struct mtd_info *mtd,
|
|
struct nand_chip *chip, uint8_t *buf)
|
|
{
|
|
int eccsize = chip->ecc.size;
|
|
int eccbytes = chip->ecc.bytes;
|
|
uint32_t *eccpos = chip->ecc.layout->eccpos;
|
|
uint8_t *p = buf;
|
|
uint8_t *oob = chip->oob_poi;
|
|
uint8_t *ecc_pos;
|
|
int stat;
|
|
|
|
/*
|
|
* Errata: ALE is incorrectly wired up to the ECC controller
|
|
* on the AP7000, so it will include the address cycles in the
|
|
* ECC calculation.
|
|
*
|
|
* Workaround: Reset the parity registers before reading the
|
|
* actual data.
|
|
*/
|
|
#if 0
|
|
if (cpu_is_at32ap7000()) {
|
|
struct atmel_nand_host *host = chip->priv;
|
|
ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
|
|
}
|
|
#endif
|
|
|
|
/* read the page */
|
|
chip->read_buf(mtd, p, eccsize);
|
|
|
|
/* move to ECC position if needed */
|
|
if (eccpos[0] != 0) {
|
|
/* This only works on large pages
|
|
* because the ECC controller waits for
|
|
* NAND_CMD_RNDOUTSTART after the
|
|
* NAND_CMD_RNDOUT.
|
|
* anyway, for small pages, the eccpos[0] == 0
|
|
*/
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
|
|
mtd->writesize + eccpos[0], -1);
|
|
}
|
|
|
|
/* the ECC controller needs to read the ECC just after the data */
|
|
ecc_pos = oob + eccpos[0];
|
|
chip->read_buf(mtd, ecc_pos, eccbytes);
|
|
|
|
/* check if there's an error */
|
|
stat = chip->ecc.correct(mtd, p, oob, NULL);
|
|
|
|
if (stat < 0)
|
|
mtd->ecc_stats.failed++;
|
|
else
|
|
mtd->ecc_stats.corrected += stat;
|
|
|
|
/* get back to oob start (end of page) */
|
|
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
|
|
|
|
/* read the oob */
|
|
chip->read_buf(mtd, oob, mtd->oobsize);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* HW ECC Correction
|
|
*
|
|
* function called after a read
|
|
*
|
|
* mtd: MTD block structure
|
|
* dat: raw data read from the chip
|
|
* read_ecc: ECC from the chip (unused)
|
|
* isnull: unused
|
|
*
|
|
* Detect and correct a 1 bit error for a page
|
|
*/
|
|
static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
|
|
u_char *read_ecc, u_char *isnull)
|
|
{
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
struct atmel_nand_host *host = nand_chip->priv;
|
|
unsigned int ecc_status;
|
|
unsigned int ecc_word, ecc_bit;
|
|
|
|
/* get the status from the Status Register */
|
|
ecc_status = ecc_readl(host->ecc, SR);
|
|
|
|
/* if there's no error */
|
|
if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
|
|
return 0;
|
|
|
|
/* get error bit offset (4 bits) */
|
|
ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
|
|
/* get word address (12 bits) */
|
|
ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
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ecc_word >>= 4;
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|
|
|
/* if there are multiple errors */
|
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if (ecc_status & ATMEL_ECC_MULERR) {
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/* check if it is a freshly erased block
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* (filled with 0xff) */
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if ((ecc_bit == ATMEL_ECC_BITADDR)
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&& (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
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/* the block has just been erased, return OK */
|
|
return 0;
|
|
}
|
|
/* it doesn't seems to be a freshly
|
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* erased block.
|
|
* We can't correct so many errors */
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dev_dbg(host->dev, "atmel_nand : multiple errors detected."
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" Unable to correct.\n");
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|
return -EIO;
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}
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|
|
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/* if there's a single bit error : we can correct it */
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if (ecc_status & ATMEL_ECC_ECCERR) {
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/* there's nothing much to do here.
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* the bit error is on the ECC itself.
|
|
*/
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dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
|
|
" Nothing to correct\n");
|
|
return 0;
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|
}
|
|
|
|
dev_dbg(host->dev, "atmel_nand : one bit error on data."
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" (word offset in the page :"
|
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" 0x%x bit offset : 0x%x)\n",
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ecc_word, ecc_bit);
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/* correct the error */
|
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if (nand_chip->options & NAND_BUSWIDTH_16) {
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/* 16 bits words */
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((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
|
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} else {
|
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/* 8 bits words */
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dat[ecc_word] ^= (1 << ecc_bit);
|
|
}
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dev_dbg(host->dev, "atmel_nand : error corrected\n");
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|
return 1;
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|
}
|
|
|
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/*
|
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* Enable HW ECC : unused on most chips
|
|
*/
|
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static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
|
|
{
|
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#if 0
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if (cpu_is_at32ap7000()) {
|
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struct nand_chip *nand_chip = mtd->priv;
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struct atmel_nand_host *host = nand_chip->priv;
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ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
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}
|
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#endif
|
|
}
|
|
|
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static int atmel_hw_nand_init_params(struct device_d *dev,
|
|
struct atmel_nand_host *host)
|
|
{
|
|
struct mtd_info *mtd = &host->mtd;
|
|
struct nand_chip *nand_chip = &host->nand_chip;
|
|
|
|
host->ecc = dev_request_mem_region(dev, 1);
|
|
if (host->ecc == NULL) {
|
|
dev_err(host->dev, "ioremap failed\n");
|
|
return -EIO;
|
|
}
|
|
|
|
/* ECC is calculated for the whole page (1 step) */
|
|
nand_chip->ecc.size = mtd->writesize;
|
|
|
|
/* set ECC page size and oob layout */
|
|
switch (mtd->writesize) {
|
|
case 512:
|
|
nand_chip->ecc.layout = &atmel_oobinfo_small;
|
|
ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
|
|
break;
|
|
case 1024:
|
|
nand_chip->ecc.layout = &atmel_oobinfo_large;
|
|
ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
|
|
break;
|
|
case 2048:
|
|
nand_chip->ecc.layout = &atmel_oobinfo_large;
|
|
ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
|
|
break;
|
|
case 4096:
|
|
nand_chip->ecc.layout = &atmel_oobinfo_large;
|
|
ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
|
|
break;
|
|
default:
|
|
/* page size not handled by HW ECC */
|
|
/* switching back to soft ECC */
|
|
nand_chip->ecc.mode = NAND_ECC_SOFT;
|
|
return 0;
|
|
}
|
|
|
|
/* set up for HW ECC */
|
|
nand_chip->ecc.calculate = atmel_nand_calculate;
|
|
nand_chip->ecc.correct = atmel_nand_correct;
|
|
nand_chip->ecc.hwctl = atmel_nand_hwctl;
|
|
nand_chip->ecc.read_page = atmel_nand_read_page;
|
|
nand_chip->ecc.bytes = 4;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Probe for the NAND device.
|
|
*/
|
|
static int __init atmel_nand_probe(struct device_d *dev)
|
|
{
|
|
struct atmel_nand_data *pdata = dev->platform_data;
|
|
struct atmel_nand_host *host;
|
|
struct mtd_info *mtd;
|
|
struct nand_chip *nand_chip;
|
|
int res = 0;
|
|
|
|
/* Allocate memory for the device structure (and zero it) */
|
|
host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
|
|
if (!host)
|
|
return -ENOMEM;
|
|
|
|
host->io_base = dev_request_mem_region(dev, 0);
|
|
|
|
mtd = &host->mtd;
|
|
nand_chip = &host->nand_chip;
|
|
host->board = pdata;
|
|
host->dev = dev;
|
|
|
|
nand_chip->priv = host; /* link the private data structures */
|
|
mtd->priv = nand_chip;
|
|
mtd->parent = dev;
|
|
|
|
/* Set address of NAND IO lines */
|
|
nand_chip->IO_ADDR_R = host->io_base;
|
|
nand_chip->IO_ADDR_W = host->io_base;
|
|
nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
|
|
|
|
if (gpio_is_valid(host->board->rdy_pin)) {
|
|
res = gpio_request(host->board->rdy_pin, "nand_rdy");
|
|
if (res < 0) {
|
|
dev_err(dev, "can't request rdy gpio %d\n",
|
|
host->board->rdy_pin);
|
|
goto err_no_card;
|
|
}
|
|
|
|
res = gpio_direction_input(host->board->rdy_pin);
|
|
if (res < 0) {
|
|
dev_err(dev,
|
|
"can't request input direction rdy gpio %d\n",
|
|
host->board->rdy_pin);
|
|
goto err_no_card;
|
|
}
|
|
|
|
nand_chip->dev_ready = atmel_nand_device_ready;
|
|
}
|
|
|
|
if (gpio_is_valid(host->board->enable_pin)) {
|
|
res = gpio_request(host->board->enable_pin, "nand_enable");
|
|
if (res < 0) {
|
|
dev_err(dev,
|
|
"can't request enable gpio %d\n",
|
|
host->board->enable_pin);
|
|
goto err_no_card;
|
|
}
|
|
|
|
res = gpio_direction_output(host->board->enable_pin, 1);
|
|
if (res < 0) {
|
|
dev_err(dev,
|
|
"can't request output direction enable gpio %d\n",
|
|
host->board->enable_pin);
|
|
goto err_no_card;
|
|
}
|
|
}
|
|
|
|
nand_chip->ecc.mode = NAND_ECC_SOFT;
|
|
|
|
if (IS_ENABLED(CONFIG_NAND_ECC_HW) &&
|
|
pdata->ecc_mode == NAND_ECC_HW) {
|
|
nand_chip->ecc.mode = NAND_ECC_HW;
|
|
}
|
|
|
|
nand_chip->chip_delay = 20; /* 20us command delay time */
|
|
|
|
if (host->board->bus_width_16) { /* 16-bit bus width */
|
|
nand_chip->options |= NAND_BUSWIDTH_16;
|
|
nand_chip->read_buf = atmel_read_buf16;
|
|
nand_chip->write_buf = atmel_write_buf16;
|
|
} else {
|
|
nand_chip->read_buf = atmel_read_buf;
|
|
nand_chip->write_buf = atmel_write_buf;
|
|
}
|
|
|
|
atmel_nand_enable(host);
|
|
|
|
if (gpio_is_valid(host->board->det_pin)) {
|
|
res = gpio_request(host->board->det_pin, "nand_det");
|
|
if (res < 0) {
|
|
dev_err(dev, "can't request det gpio %d\n",
|
|
host->board->det_pin);
|
|
goto err_no_card;
|
|
}
|
|
|
|
res = gpio_direction_input(host->board->det_pin);
|
|
if (res < 0) {
|
|
dev_err(dev,
|
|
"can't request input direction det gpio %d\n",
|
|
host->board->det_pin);
|
|
goto err_no_card;
|
|
}
|
|
|
|
if (gpio_get_value(host->board->det_pin)) {
|
|
printk("No SmartMedia card inserted.\n");
|
|
res = -ENXIO;
|
|
goto err_no_card;
|
|
}
|
|
}
|
|
|
|
if (host->board->on_flash_bbt) {
|
|
printk(KERN_INFO "atmel_nand: Use On Flash BBT\n");
|
|
nand_chip->options |= NAND_USE_FLASH_BBT;
|
|
}
|
|
|
|
|
|
/* first scan to find the device and get the page size */
|
|
if (nand_scan_ident(mtd, 1)) {
|
|
res = -ENXIO;
|
|
goto err_scan_ident;
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_NAND_ECC_HW) &&
|
|
nand_chip->ecc.mode == NAND_ECC_HW) {
|
|
if (IS_ENABLED(CONFIG_NAND_ATMEL_PMECC))
|
|
res = atmel_pmecc_nand_init_params(dev, host);
|
|
else
|
|
res = atmel_hw_nand_init_params(dev, host);
|
|
|
|
if (res != 0)
|
|
goto err_hw_ecc;
|
|
}
|
|
|
|
/* second phase scan */
|
|
if (nand_scan_tail(mtd)) {
|
|
res = -ENXIO;
|
|
goto err_scan_tail;
|
|
}
|
|
|
|
add_mtd_device(mtd, "nand");
|
|
|
|
if (!res)
|
|
return res;
|
|
|
|
nand_release(mtd);
|
|
err_scan_tail:
|
|
err_hw_ecc:
|
|
err_scan_ident:
|
|
err_no_card:
|
|
atmel_nand_disable(host);
|
|
kfree(host);
|
|
return res;
|
|
}
|
|
|
|
static struct driver_d atmel_nand_driver = {
|
|
.name = "atmel_nand",
|
|
.probe = atmel_nand_probe,
|
|
};
|
|
device_platform_driver(atmel_nand_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Rick Bronson");
|
|
MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
|