394 lines
12 KiB
C
394 lines
12 KiB
C
/*
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* Copyright (C) 2012 Jan Luebbe <j.luebbe@pengutronix.de>
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*
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* Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
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*
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* Driver for McSPI controller on OMAP3. Based on davinci_spi.c
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* Parts taken from linux/drivers/spi/omap2_mcspi.c
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* Copyright (C) 2005, 2006 Nokia Corporation
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*
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* Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <clock.h>
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#include <errno.h>
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#include <spi/spi.h>
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#include <malloc.h>
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#include <io.h>
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#include "omap3_spi.h"
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#define WORD_LEN 8
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#define SPI_WAIT_TIMEOUT MSECOND
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#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
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#define SPI_XFER_END 0x02 /* Deassert CS after transfer */
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static void spi_reset(struct spi_master *master)
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{
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struct omap3_spi_master *omap3_master = container_of(master, struct omap3_spi_master, master);
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void __iomem *regs = omap3_master->regs;
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unsigned int tmp;
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writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, regs + OMAP3_MCSPI_SYSCONFIG);
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do {
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tmp = readl(regs + OMAP3_MCSPI_SYSSTATUS);
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} while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
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writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
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OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
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OMAP3_MCSPI_SYSCONFIG_SMARTIDLE,
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regs + OMAP3_MCSPI_SYSCONFIG);
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writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, regs + OMAP3_MCSPI_WAKEUPENABLE);
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}
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int spi_claim_bus(struct spi_device *spi)
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{
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struct spi_master *master = spi->master;
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struct omap3_spi_master *omap3_master = container_of(master, struct omap3_spi_master, master);
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void __iomem *regs = omap3_master->regs;
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unsigned int conf, div = 0;
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/* McSPI global module configuration */
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/*
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* setup when switching from (reset default) slave mode
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* to single-channel master mode
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*/
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conf = readl(regs + OMAP3_MCSPI_MODULCTRL);
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conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
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conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
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writel(conf, regs + OMAP3_MCSPI_MODULCTRL);
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/* McSPI individual channel configuration */
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/* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
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if (spi->max_speed_hz) {
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while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
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> spi->max_speed_hz)
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div++;
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} else {
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div = 0xC;
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}
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conf = readl(regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
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* REVISIT: this controller could support SPI_3WIRE mode.
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*/
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conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
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conf |= OMAP3_MCSPI_CHCONF_DPE0;
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/* wordlength */
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conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
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conf |= (WORD_LEN - 1) << 7;
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/* set chipselect polarity; manage with FORCE */
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if (!(spi->mode & SPI_CS_HIGH))
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conf |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
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else
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conf &= ~OMAP3_MCSPI_CHCONF_EPOL;
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/* set clock divisor */
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conf &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
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conf |= div << 2;
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/* set SPI mode 0..3 */
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if (spi->mode & SPI_CPOL)
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conf |= OMAP3_MCSPI_CHCONF_POL;
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else
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conf &= ~OMAP3_MCSPI_CHCONF_POL;
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if (spi->mode & SPI_CPHA)
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conf |= OMAP3_MCSPI_CHCONF_PHA;
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else
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conf &= ~OMAP3_MCSPI_CHCONF_PHA;
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/* Transmit & receive mode */
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conf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
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writel(conf, regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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readl(regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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return 0;
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}
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int omap3_spi_write(struct spi_device *spi, unsigned int len, const u8 *txp,
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unsigned long flags)
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{
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struct spi_master *master = spi->master;
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struct omap3_spi_master *omap3_master = container_of(master, struct omap3_spi_master, master);
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void __iomem *regs = omap3_master->regs;
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int i;
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uint64_t timer_start;
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int chconf = readl(regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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if (flags & SPI_XFER_BEGIN)
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writel(OMAP3_MCSPI_CHCTRL_EN,
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regs + OMAP3_MCSPI_CHCTRL0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
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chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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writel(chconf, regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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readl(regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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for (i = 0; i < len; i++) {
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/* wait till TX register is empty (TXS == 1) */
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timer_start = get_time_ns();
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while (!(readl(regs + OMAP3_MCSPI_CHSTAT0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE) &
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OMAP3_MCSPI_CHSTAT_TXS)) {
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if (is_timeout(timer_start, SPI_WAIT_TIMEOUT)) {
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printf("SPI TXS timed out, status=0x%08x\n",
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readl(regs + OMAP3_MCSPI_CHSTAT0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE));
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return -ETIMEDOUT;
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}
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}
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/* write the data */
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writel(txp[i], regs + OMAP3_MCSPI_TX0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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}
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if (flags & SPI_XFER_END) {
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/* wait to finish of transfer */
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while (!(readl(regs + OMAP3_MCSPI_CHSTAT0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE) &
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OMAP3_MCSPI_CHSTAT_EOT));
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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writel(chconf, regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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writel(0, regs + OMAP3_MCSPI_CHCTRL0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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}
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while (!(readl(regs + OMAP3_MCSPI_CHSTAT0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE) &
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OMAP3_MCSPI_CHSTAT_TXS));
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while (!(readl(regs + OMAP3_MCSPI_CHSTAT0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE) &
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OMAP3_MCSPI_CHSTAT_EOT));
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return 0;
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}
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int omap3_spi_read(struct spi_device *spi, unsigned int len, u8 *rxp,
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unsigned long flags)
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{
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struct spi_master *master = spi->master;
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struct omap3_spi_master *omap3_master = container_of(master, struct omap3_spi_master, master);
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void __iomem *regs = omap3_master->regs;
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int i;
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uint64_t timer_start;
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int chconf = readl(regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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if (flags & SPI_XFER_BEGIN)
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writel(OMAP3_MCSPI_CHCTRL_EN,
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regs + OMAP3_MCSPI_CHCTRL0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
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chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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writel(chconf, regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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readl(regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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writel(0, regs + OMAP3_MCSPI_TX0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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for (i = 0; i < len; i++) {
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/* wait till RX register contains data (RXS == 1) */
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timer_start = get_time_ns();
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while (!(readl(regs + OMAP3_MCSPI_CHSTAT0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE) &
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OMAP3_MCSPI_CHSTAT_RXS)) {
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if (is_timeout(timer_start, SPI_WAIT_TIMEOUT)) {
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printf("SPI RXS timed out, status=0x%08x\n",
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readl(regs + OMAP3_MCSPI_CHSTAT0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE));
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return -ETIMEDOUT;
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}
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}
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/* read the data */
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rxp[i] = readl(regs + OMAP3_MCSPI_RX0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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}
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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writel(chconf, regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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readl(regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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writel(0, regs + OMAP3_MCSPI_CHCTRL0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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}
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return 0;
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}
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int spi_xfer(struct spi_device *spi, struct spi_transfer *t, unsigned long flags)
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{
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struct spi_master *master = spi->master;
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struct omap3_spi_master *omap3_master = container_of(master, struct omap3_spi_master, master);
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void __iomem *regs = omap3_master->regs;
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unsigned int len = t->len;
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int ret;
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const u8 *txp = t->tx_buf; /* can be NULL for read operation */
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u8 *rxp = t->rx_buf; /* can be NULL for write operation */
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if (len == 0) { /* only change CS */
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int chconf = readl(regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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if (flags & SPI_XFER_BEGIN) {
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writel(OMAP3_MCSPI_CHCTRL_EN,
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regs + OMAP3_MCSPI_CHCTRL0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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chconf |= OMAP3_MCSPI_CHCONF_FORCE;
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writel(chconf,
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regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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readl(regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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}
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if (flags & SPI_XFER_END) {
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chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
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writel(chconf,
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regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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writel(0, regs + OMAP3_MCSPI_CHCTRL0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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readl(regs + OMAP3_MCSPI_CHCONF0 + spi->chip_select * OMAP3_MCSPI_CH_SIZE);
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}
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ret = 0;
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} else if ((t->tx_buf != NULL) && (t->rx_buf != NULL)) {
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printf("SPI error: full duplex unsupported\n");
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ret = -EINVAL;
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} else if (t->tx_buf != NULL) {
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ret = omap3_spi_write(spi, len, txp, flags);
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} else if (t->rx_buf != NULL) {
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ret = omap3_spi_read(spi, len, rxp, flags);
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} else {
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printf("SPI error: neither tx_buf nor rx_buf set\n");
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ret = -EINVAL;
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}
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return ret;
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}
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static int omap3_spi_transfer(struct spi_device *spi, struct spi_message *mesg)
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{
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struct spi_master *master = spi->master;
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struct spi_transfer *t, *t_first, *t_last = NULL;
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unsigned long flags;
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int ret = 0;
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ret = spi_claim_bus(spi);
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if (ret)
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return ret;
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if (list_empty(&mesg->transfers))
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return 0;
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t_first = list_first_entry(&mesg->transfers, struct spi_transfer, transfer_list);
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t_last = list_last_entry(&mesg->transfers, struct spi_transfer, transfer_list);
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mesg->actual_length = 0;
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dev_dbg(master->dev, "transfer start actual_length=%i\n", mesg->actual_length);
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list_for_each_entry(t, &mesg->transfers, transfer_list) {
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dev_dbg(master->dev,
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" xfer %p: len %u tx %p rx %p\n",
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t, t->len, t->tx_buf, t->rx_buf);
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flags = 0;
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if (t == t_first)
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flags |= SPI_XFER_BEGIN;
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if (t == t_last)
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flags |= SPI_XFER_END;
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ret = spi_xfer(spi, t, flags);
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if (ret < 0)
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return ret;
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mesg->actual_length += t->len;
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}
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dev_dbg(master->dev, "transfer done actual_length=%i\n", mesg->actual_length);
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return ret;
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}
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static int omap3_spi_setup(struct spi_device *spi)
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{
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struct spi_master *master = spi->master;
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if (((master->bus_num == 1) && (spi->chip_select > 3)) ||
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((master->bus_num == 2) && (spi->chip_select > 1)) ||
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((master->bus_num == 3) && (spi->chip_select > 1)) ||
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((master->bus_num == 4) && (spi->chip_select > 0))) {
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printf("SPI error: unsupported chip select %i \
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on bus %i\n", spi->chip_select, master->bus_num);
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return -EINVAL;
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}
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if (spi->max_speed_hz > OMAP3_MCSPI_MAX_FREQ) {
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printf("SPI error: unsupported frequency %i Hz. \
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Max frequency is 48 Mhz\n", spi->max_speed_hz);
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return -EINVAL;
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}
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if (spi->mode > SPI_MODE_3) {
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printf("SPI error: unsupported SPI mode %i\n", spi->mode);
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return -EINVAL;
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}
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return 0;
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}
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static int omap3_spi_probe(struct device_d *dev)
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{
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struct spi_master *master;
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struct omap3_spi_master *omap3_master;
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omap3_master = xzalloc(sizeof(*omap3_master));
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master = &omap3_master->master;
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master->dev = dev;
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/*
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* OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
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* with different number of chip selects (CS, channels):
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* McSPI1 has 4 CS (bus 1, cs 0 - 3)
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* McSPI2 has 2 CS (bus 2, cs 0 - 1)
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* McSPI3 has 2 CS (bus 3, cs 0 - 1)
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* McSPI4 has 1 CS (bus 4, cs 0)
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*
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* The board code has to make sure that it does not use
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* invalid buses or chip selects.
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*/
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master->bus_num = dev->id;
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master->num_chipselect = 4;
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master->setup = omap3_spi_setup;
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master->transfer = omap3_spi_transfer;
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omap3_master->regs = dev_request_mem_region(dev, 0);;
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spi_reset(master);
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spi_register_master(master);
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return 0;
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}
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static struct driver_d omap3_spi_driver = {
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.name = "omap3_spi",
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.probe = omap3_spi_probe,
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};
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device_platform_driver(omap3_spi_driver);
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