e0965c4d56
When booting from NAND, its important to know the correct page size. When the NAND is used as the boot source, four dedicated pins are used to configure the correct page size and address cycles. These pins can be read back in one of the NFC registers to parametrize the load function. This patch also extends the read routine to support more than four address cycles on demand. BTW: At least some mini2440s are misconfigured to use five address cycles for a NAND device that is known to need only four address cycles. In this case the vendor is at our side: This NAND simply ignores any additional address cycles than required. Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> |
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| .. | ||
| include/mach | ||
| Kconfig | ||
| Makefile | ||
| generic.c | ||
| gpio-s3c24x0.c | ||
| lowlevel-init.S | ||