The fixed clocks are registered from devicetree. Therefore the code path is not needed, but would instead register the clocks twice, which leads to the error message: clk_register clk f2s_periph_ref_clk is already registered, skipping! of_clk_init: failed to init clock for /soc/clkmgr@ffd04000/clocks/f2s_periph_ref_clk: 1 clk_register clk osc1 is already registered, skipping! of_clk_init: failed to init clock for /soc/clkmgr@ffd04000/clocks/osc1: 1 Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
414 lines
9.4 KiB
C
414 lines
9.4 KiB
C
/*
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* Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <linux/clk.h>
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#include <io.h>
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#include <malloc.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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/* Clock Manager offsets */
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#define CLKMGR_CTRL 0x0
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#define CLKMGR_BYPASS 0x4
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#define CLKMGR_L4SRC 0x70
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#define CLKMGR_PERPLL_SRC 0xAC
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/* Clock bypass bits */
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#define MAINPLL_BYPASS (1<<0)
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#define SDRAMPLL_BYPASS (1<<1)
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#define SDRAMPLL_SRC_BYPASS (1<<2)
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#define PERPLL_BYPASS (1<<3)
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#define PERPLL_SRC_BYPASS (1<<4)
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#define SOCFPGA_PLL_BG_PWRDWN 0
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#define SOCFPGA_PLL_EXT_ENA 1
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#define SOCFPGA_PLL_PWR_DOWN 2
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#define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8
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#define SOCFPGA_PLL_DIVF_SHIFT 3
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#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
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#define SOCFPGA_PLL_DIVQ_SHIFT 16
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#define SOCFGPA_MAX_PARENTS 3
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#define SOCFPGA_L4_MP_CLK "l4_mp_clk"
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#define SOCFPGA_L4_SP_CLK "l4_sp_clk"
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#define SOCFPGA_NAND_CLK "nand_clk"
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#define SOCFPGA_NAND_X_CLK "nand_x_clk"
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#define SOCFPGA_MMC_CLK "sdmmc_clk"
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#define SOCFPGA_DB_CLK "gpio_db_clk"
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#define div_mask(width) ((1 << (width)) - 1)
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#define streq(a, b) (strcmp((a), (b)) == 0)
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static void __iomem *clk_mgr_base_addr;
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struct clk_pll {
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struct clk clk;
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const char *parent;
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unsigned regofs;
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};
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static unsigned long clk_pll_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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struct clk_pll *pll = container_of(clk, struct clk_pll, clk);
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unsigned long divf, divq, vco_freq, reg;
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unsigned long bypass;
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reg = readl(clk_mgr_base_addr + pll->regofs);
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bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
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if (bypass & MAINPLL_BYPASS)
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return parent_rate;
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divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
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divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
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vco_freq = parent_rate * (divf + 1);
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return vco_freq / (1 + divq);
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}
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static struct clk_ops clk_pll_ops = {
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.recalc_rate = clk_pll_recalc_rate,
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};
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static struct clk *socfpga_pll_clk(struct device_node *node)
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{
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struct clk_pll *pll;
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int ret;
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pll = xzalloc(sizeof(*pll));
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pll->parent = of_clk_get_parent_name(node, 0);
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if (!pll->parent)
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return ERR_PTR(-EINVAL);
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pll->clk.parent_names = &pll->parent;
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pll->clk.num_parents = 1;
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pll->clk.name = xstrdup(node->name);
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pll->clk.ops = &clk_pll_ops;
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of_property_read_u32(node, "reg", &pll->regofs);
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ret = clk_register(&pll->clk);
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if (ret) {
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free(pll);
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return ERR_PTR(ret);
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}
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return &pll->clk;
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}
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struct clk_periph {
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struct clk clk;
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const char *parent;
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unsigned regofs;
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unsigned int fixed_div;
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};
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static unsigned long clk_periph_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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struct clk_periph *periph = container_of(clk, struct clk_periph, clk);
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u32 div;
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if (periph->fixed_div)
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div = periph->fixed_div;
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else
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div = ((readl(clk_mgr_base_addr + periph->regofs) & 0x1ff) + 1);
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return parent_rate / div;
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}
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static struct clk_ops clk_periph_ops = {
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.recalc_rate = clk_periph_recalc_rate,
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};
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static struct clk *socfpga_periph_clk(struct device_node *node)
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{
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struct clk_periph *periph;
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int ret;
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periph = xzalloc(sizeof(*periph));
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periph->parent = of_clk_get_parent_name(node, 0);
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if (!periph->parent)
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return ERR_PTR(-EINVAL);
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periph->clk.parent_names = &periph->parent;
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periph->clk.num_parents = 1;
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periph->clk.name = xstrdup(node->name);
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periph->clk.ops = &clk_periph_ops;
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of_property_read_u32(node, "reg", &periph->regofs);
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of_property_read_u32(node, "fixed-divider", &periph->fixed_div);
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ret = clk_register(&periph->clk);
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if (ret) {
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free(periph);
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return ERR_PTR(ret);
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}
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return &periph->clk;
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}
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struct clk_socfpga {
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struct clk clk;
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const char *parent;
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void __iomem *reg;
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void __iomem *div_reg;
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unsigned int fixed_div;
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unsigned int bit_idx;
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unsigned int shift;
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unsigned int width;
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const char *parent_names[SOCFGPA_MAX_PARENTS];
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};
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static int clk_socfpga_enable(struct clk *clk)
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{
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struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
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u32 val;
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val = readl(cs->reg);
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val |= 1 << cs->shift;
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writel(val, cs->reg);
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return 0;
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}
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static void clk_socfpga_disable(struct clk *clk)
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{
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struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
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u32 val;
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val = readl(cs->reg);
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val &= ~(1 << cs->shift);
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writel(val, cs->reg);
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}
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static int clk_socfpga_is_enabled(struct clk *clk)
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{
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struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
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u32 val;
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val = readl(cs->reg);
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if (val & (1 << cs->shift))
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return 1;
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else
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return 0;
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}
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static unsigned long clk_socfpga_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
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u32 div = 1, val;
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if (cs->fixed_div) {
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div = cs->fixed_div;
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} else if (cs->div_reg) {
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val = readl(cs->div_reg) >> cs->shift;
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val &= div_mask(cs->width);
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if (streq(clk->name, SOCFPGA_DB_CLK))
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div = val + 1;
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else
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div = (1 << val);
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}
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return parent_rate / div;
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}
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static int clk_socfpga_get_parent(struct clk *clk)
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{
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u32 perpll_src;
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u32 l4_src;
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if (streq(clk->name, SOCFPGA_L4_MP_CLK)) {
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l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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return l4_src &= 0x1;
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}
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if (streq(clk->name, SOCFPGA_L4_SP_CLK)) {
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l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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return !!(l4_src & 2);
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}
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perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
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if (streq(clk->name, SOCFPGA_MMC_CLK))
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return perpll_src &= 0x3;
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if (streq(clk->name, SOCFPGA_NAND_CLK) ||
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streq(clk->name, SOCFPGA_NAND_X_CLK))
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return (perpll_src >> 2) & 3;
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/* QSPI clock */
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return (perpll_src >> 4) & 3;
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}
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static int clk_socfpga_set_parent(struct clk *clk, u8 parent)
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{
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u32 src_reg;
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if (streq(clk->name, SOCFPGA_L4_MP_CLK)) {
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src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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src_reg &= ~0x1;
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src_reg |= parent;
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writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
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} else if (streq(clk->name, SOCFPGA_L4_SP_CLK)) {
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src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
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src_reg &= ~0x2;
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src_reg |= (parent << 1);
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writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
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} else {
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src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
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if (streq(clk->name, SOCFPGA_MMC_CLK)) {
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src_reg &= ~0x3;
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src_reg |= parent;
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} else if (streq(clk->name, SOCFPGA_NAND_CLK) ||
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streq(clk->name, SOCFPGA_NAND_X_CLK)) {
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src_reg &= ~0xC;
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src_reg |= (parent << 2);
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} else {/* QSPI clock */
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src_reg &= ~0x30;
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src_reg |= (parent << 4);
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}
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writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
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}
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return 0;
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}
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static struct clk_ops clk_socfpga_ops = {
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.recalc_rate = clk_socfpga_recalc_rate,
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.enable = clk_socfpga_enable,
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.disable = clk_socfpga_disable,
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.is_enabled = clk_socfpga_is_enabled,
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.get_parent = clk_socfpga_get_parent,
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.set_parent = clk_socfpga_set_parent,
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};
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static struct clk *socfpga_gate_clk(struct device_node *node)
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{
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u32 clk_gate[2];
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u32 div_reg[3];
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u32 fixed_div;
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struct clk_socfpga *cs;
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int ret;
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int i = 0;
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cs = xzalloc(sizeof(*cs));
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ret = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
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if (ret)
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clk_gate[0] = 0;
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if (clk_gate[0]) {
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cs->reg = clk_mgr_base_addr + clk_gate[0];
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cs->bit_idx = clk_gate[1];
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}
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ret = of_property_read_u32(node, "fixed-divider", &fixed_div);
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if (ret)
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cs->fixed_div = 0;
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else
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cs->fixed_div = fixed_div;
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ret = of_property_read_u32_array(node, "div-reg", div_reg, 3);
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if (!ret) {
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cs->div_reg = clk_mgr_base_addr + div_reg[0];
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cs->shift = div_reg[1];
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cs->width = div_reg[2];
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}
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for (i = 0; i < SOCFGPA_MAX_PARENTS; i++) {
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cs->parent_names[i] = of_clk_get_parent_name(node, i);
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if (!cs->parent_names[i])
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break;
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}
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cs->clk.parent_names = cs->parent_names;
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cs->clk.num_parents = i;
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cs->clk.name = xstrdup(node->name);
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cs->clk.ops = &clk_socfpga_ops;
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ret = clk_register(&cs->clk);
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if (ret) {
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free(cs);
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return ERR_PTR(ret);
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}
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return &cs->clk;
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}
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static void socfpga_register_clocks(struct device_d *dev, struct device_node *node)
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{
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struct device_node *child;
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struct clk *clk;
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for_each_child_of_node(node, child) {
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socfpga_register_clocks(dev, child);
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}
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if (of_device_is_compatible(node, "altr,socfpga-pll-clock"))
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clk = socfpga_pll_clk(node);
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else if (of_device_is_compatible(node, "altr,socfpga-perip-clk"))
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clk = socfpga_periph_clk(node);
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else if (of_device_is_compatible(node, "altr,socfpga-gate-clk"))
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clk = socfpga_gate_clk(node);
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else
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return;
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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}
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static int socfpga_ccm_probe(struct device_d *dev)
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{
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void __iomem *regs;
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struct device_node *clknode;
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regs = dev_request_mem_region(dev, 0);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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clk_mgr_base_addr = regs;
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clknode = of_get_child_by_name(dev->device_node, "clocks");
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if (!clknode)
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return -EINVAL;
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socfpga_register_clocks(dev, clknode);
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return 0;
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}
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static __maybe_unused struct of_device_id socfpga_ccm_dt_ids[] = {
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{
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.compatible = "altr,clk-mgr",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d socfpga_ccm_driver = {
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.probe = socfpga_ccm_probe,
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.name = "socfpga-ccm",
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.of_compatible = DRV_OF_COMPAT(socfpga_ccm_dt_ids),
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};
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static int socfpga_ccm_init(void)
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{
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return platform_driver_register(&socfpga_ccm_driver);
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}
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core_initcall(socfpga_ccm_init);
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