This adds device tree support for the stm serial driver. This driver really is a AMBA primecell, so the amba-pl011 could be used. However, the current code tries to get the apb_pclk before the clocks are registered, so this does not work. Use the stm driver instead until a solution is found. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
207 lines
4.9 KiB
C
207 lines
4.9 KiB
C
/*
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* (C) Copyright 2010 Juergen Beisert - Pengutronix
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*
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* This code was inspired by some patches made for u-boot covered by:
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* (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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/*
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* Note: This is the driver for the debug UART. There is
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* only one of these UARTs on the Freescale/SigmaTel parts
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*/
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#include <common.h>
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#include <init.h>
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#include <notifier.h>
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#include <gpio.h>
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#include <io.h>
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#include <malloc.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <mach/clock.h>
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#define UARTDBGDR 0x00
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#define UARTDBGFR 0x18
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# define TXFE (1 << 7)
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# define TXFF (1 << 5)
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# define RXFE (1 << 4)
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#define UARTDBGIBRD 0x24
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#define UARTDBGFBRD 0x28
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#define UARTDBGLCR_H 0x2c
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# define WLEN8 (3 << 5)
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# define WLEN7 (2 << 5)
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# define WLEN6 (1 << 5)
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# define WLEN5 (0 << 5)
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# define FEN (1 << 4)
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#define UARTDBGCR 0x30
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# define UARTEN (1 << 0)
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# define TXE (1 << 8)
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# define RXE (1 << 9)
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#define UARTDBGIMSC 0x38
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struct stm_priv {
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struct console_device cdev;
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int baudrate;
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struct notifier_block notify;
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void __iomem *base;
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struct clk *clk;
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};
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static void stm_serial_putc(struct console_device *cdev, char c)
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{
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struct stm_priv *priv = container_of(cdev, struct stm_priv, cdev);
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/* Wait for room in TX FIFO */
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while (readl(priv->base + UARTDBGFR) & TXFF)
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;
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writel(c, priv->base + UARTDBGDR);
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}
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static int stm_serial_tstc(struct console_device *cdev)
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{
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struct stm_priv *priv = container_of(cdev, struct stm_priv, cdev);
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/* Check if RX FIFO is not empty */
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return !(readl(priv->base + UARTDBGFR) & RXFE);
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}
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static int stm_serial_getc(struct console_device *cdev)
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{
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struct stm_priv *priv = container_of(cdev, struct stm_priv, cdev);
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/* Wait while TX FIFO is empty */
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while (readl(priv->base + UARTDBGFR) & RXFE)
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;
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return readl(priv->base + UARTDBGDR) & 0xff;
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}
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static void stm_serial_flush(struct console_device *cdev)
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{
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struct stm_priv *priv = container_of(cdev, struct stm_priv, cdev);
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/* Wait for TX FIFO empty */
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while (!(readl(priv->base + UARTDBGFR) & TXFE))
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;
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}
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static int stm_serial_setbaudrate(struct console_device *cdev, int new_baudrate)
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{
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struct stm_priv *priv = container_of(cdev, struct stm_priv, cdev);
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uint32_t cr, lcr_h, quot;
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/* Disable everything */
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cr = readl(priv->base + UARTDBGCR);
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writel(0, priv->base + UARTDBGCR);
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/* Calculate and set baudrate */
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quot = (clk_get_rate(priv->clk) * 4) / new_baudrate;
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writel(quot & 0x3f, priv->base + UARTDBGFBRD);
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writel(quot >> 6, priv->base + UARTDBGIBRD);
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/* Set 8n1 mode, enable FIFOs */
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lcr_h = WLEN8 | FEN;
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writel(lcr_h, priv->base + UARTDBGLCR_H);
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/* Re-enable debug UART */
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writel(cr, priv->base + UARTDBGCR);
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priv->baudrate = new_baudrate;
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return 0;
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}
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static int stm_clocksource_clock_change(struct notifier_block *nb, unsigned long event, void *data)
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{
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struct stm_priv *priv = container_of(nb, struct stm_priv, notify);
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return stm_serial_setbaudrate(&priv->cdev, priv->baudrate);
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}
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static int stm_serial_init_port(struct stm_priv *priv)
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{
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/* Disable UART */
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writel(0, priv->base + UARTDBGCR);
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/* Mask interrupts */
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writel(0, priv->base + UARTDBGIMSC);
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return 0;
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}
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static int stm_serial_probe(struct device_d *dev)
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{
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struct stm_priv *priv;
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struct console_device *cdev;
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priv = xzalloc(sizeof *priv);
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cdev = &priv->cdev;
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cdev->tstc = stm_serial_tstc;
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cdev->putc = stm_serial_putc;
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cdev->getc = stm_serial_getc;
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cdev->flush = stm_serial_flush;
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cdev->setbrg = stm_serial_setbaudrate;
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cdev->dev = dev;
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dev->priv = priv;
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priv->base = dev_request_mem_region(dev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->clk = clk_get(dev, NULL);
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if (IS_ERR(priv->clk))
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return PTR_ERR(priv->clk);
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stm_serial_init_port(priv);
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stm_serial_setbaudrate(cdev, CONFIG_BAUDRATE);
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/* Enable UART */
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writel(TXE | RXE | UARTEN, priv->base + UARTDBGCR);
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console_register(cdev);
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priv->notify.notifier_call = stm_clocksource_clock_change;
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clock_register_client(&priv->notify);
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return 0;
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}
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static void stm_serial_remove(struct device_d *dev)
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{
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struct stm_priv *priv = dev->priv;
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stm_serial_flush(&priv->cdev);
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console_unregister(&priv->cdev);
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free(priv);
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}
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static __maybe_unused struct of_device_id stm_serial_dt_ids[] = {
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{
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.compatible = "arm,pl011",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d stm_serial_driver = {
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.name = "stm_serial",
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.probe = stm_serial_probe,
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.remove = stm_serial_remove,
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.of_compatible = DRV_OF_COMPAT(stm_serial_dt_ids),
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};
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console_platform_driver(stm_serial_driver);
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