This better separates the DMA from the MMU functionality. Also move all drivers that only depends on asm/mmu.h for the alloc functions over to the common header. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
254 lines
7.7 KiB
C
254 lines
7.7 KiB
C
/*
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* Driver for AT91/AT32 LCD Controller
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <io.h>
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#include <init.h>
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#include <mach/hardware.h>
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#include <mach/io.h>
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#include <mach/cpu.h>
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#include <errno.h>
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#include <linux/clk.h>
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#include "atmel_lcdfb.h"
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/* configurable parameters */
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#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
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#define ATMEL_LCDC_DMA_BURST_LEN 8 /* words */
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#define ATMEL_LCDC_FIFO_SIZE 512 /* words */
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static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
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{
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unsigned long value;
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if (!(cpu_is_at91sam9261() || cpu_is_at91sam9g10()
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|| cpu_is_at32ap7000()))
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return xres;
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value = xres;
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if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
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/* STN display */
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if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR)
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value *= 3;
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if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
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|| ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
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&& (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
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value = DIV_ROUND_UP(value, 4);
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else
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value = DIV_ROUND_UP(value, 8);
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}
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return value;
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}
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static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo, u32 flags)
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{
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/* Turn off the LCD controller and the DMA controller */
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lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
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sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
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/* Wait for the LCDC core to become idle */
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while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
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mdelay(10);
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lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
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if (flags & ATMEL_LCDC_STOP_NOWAIT)
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return;
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/* Wait for DMA engine to become idle... */
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while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
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mdelay(10);
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}
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static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
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{
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struct atmel_lcdfb_platform_data *pdata = sinfo->pdata;
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lcdc_writel(sinfo, ATMEL_LCDC_DMACON, pdata->default_dmacon);
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lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
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(pdata->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
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| ATMEL_LCDC_PWR);
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}
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static void atmel_lcdfb_update_dma(struct fb_info *info)
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{
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struct atmel_lcdfb_info *sinfo = info->priv;
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unsigned long dma_addr;
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dma_addr = (unsigned long)info->screen_base;
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dma_addr &= ~3UL;
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/* Set framebuffer DMA base address and pixel offset */
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lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
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}
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static void atmel_lcdfb_limit_screeninfo(struct fb_videomode *mode)
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{
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/* Saturate vertical and horizontal timings at maximum values */
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mode->vsync_len = min_t(u32, mode->vsync_len,
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(ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
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mode->upper_margin = min_t(u32, mode->upper_margin,
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ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
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mode->lower_margin = min_t(u32, mode->lower_margin,
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ATMEL_LCDC_VFP);
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mode->right_margin = min_t(u32, mode->right_margin,
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(ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
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mode->hsync_len = min_t(u32, mode->hsync_len,
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(ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
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mode->left_margin = min_t(u32, mode->left_margin,
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ATMEL_LCDC_HBP + 1);
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}
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static void atmel_lcdfb_setup_core(struct fb_info *info)
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{
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struct atmel_lcdfb_info *sinfo = info->priv;
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struct atmel_lcdfb_platform_data *pdata = sinfo->pdata;
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struct fb_videomode *mode = info->mode;
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unsigned long clk_value_khz;
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unsigned long pix_factor = 2;
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unsigned long hozval_linesz;
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unsigned long value;
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/* ...set frame size and burst length = 8 words (?) */
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value = (mode->yres * mode->xres * info->bits_per_pixel) / 32;
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value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
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lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
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/* Set pixel clock */
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if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es())
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pix_factor = 1;
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clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
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value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(mode->pixclock));
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if (value < pix_factor) {
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dev_notice(&info->dev, "Bypassing pixel clock divider\n");
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lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
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} else {
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value = (value / pix_factor) - 1;
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dev_dbg(&info->dev, " * programming CLKVAL = 0x%08lx\n",
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value);
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lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
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value << ATMEL_LCDC_CLKVAL_OFFSET);
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mode->pixclock =
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KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
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dev_dbg(&info->dev, " updated pixclk: %lu KHz\n",
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PICOS2KHZ(mode->pixclock));
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}
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/* Initialize control register 2 */
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value = pdata->default_lcdcon2;
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if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
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value |= ATMEL_LCDC_INVLINE_INVERTED;
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if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
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value |= ATMEL_LCDC_INVFRAME_INVERTED;
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switch (info->bits_per_pixel) {
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case 1: value |= ATMEL_LCDC_PIXELSIZE_1; break;
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case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
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case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
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case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
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case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
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case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
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case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
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default: BUG(); break;
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}
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dev_dbg(&info->dev, " * LCDCON2 = %08lx\n", value);
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lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
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/* Vertical timing */
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value = (mode->vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
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value |= mode->upper_margin << ATMEL_LCDC_VBP_OFFSET;
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value |= mode->lower_margin;
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dev_dbg(&info->dev, " * LCDTIM1 = %08lx\n", value);
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lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
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/* Horizontal timing */
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value = (mode->right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
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value |= (mode->hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
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value |= (mode->left_margin - 1);
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dev_dbg(&info->dev, " * LCDTIM2 = %08lx\n", value);
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lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
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/* Horizontal value (aka line size) */
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hozval_linesz = compute_hozval(mode->xres,
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lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
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/* Display size */
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value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
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value |= mode->yres - 1;
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dev_dbg(&info->dev, " * LCDFRMCFG = %08lx\n", value);
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lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
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/* FIFO Threshold: Use formula from data sheet */
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value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
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lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
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/* Toggle LCD_MODE every frame */
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lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
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/* Disable all interrupts */
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lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
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/* Enable FIFO & DMA errors */
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lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
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/* ...wait for DMA engine to become idle... */
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while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
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mdelay(10);
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}
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static void atmel_lcdfb_init_contrast(struct atmel_lcdfb_info *sinfo)
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{
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unsigned long value;
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value = ATMEL_LCDC_PS_DIV8 |
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ATMEL_LCDC_POL_POSITIVE |
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ATMEL_LCDC_ENA_PWMENABLE;
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lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, value);
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lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
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}
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struct atmel_lcdfb_devdata atmel_lcdfb_data = {
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.start = atmel_lcdfb_start,
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.stop = atmel_lcdfb_stop,
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.update_dma = atmel_lcdfb_update_dma,
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.setup_core = atmel_lcdfb_setup_core,
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.init_contrast = atmel_lcdfb_init_contrast,
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.limit_screeninfo = atmel_lcdfb_limit_screeninfo,
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};
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static int atmel_lcdc_probe(struct device_d *dev)
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{
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return atmel_lcdc_register(dev, &atmel_lcdfb_data);
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}
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static struct driver_d atmel_lcdc_driver = {
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.name = "atmel_lcdfb",
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.probe = atmel_lcdc_probe,
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};
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device_platform_driver(atmel_lcdc_driver);
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