The reference manual (for the i.MX25 in my case) states: This field must start at a location that enables a complete picture to be stored in a 4 Mbyte memory boundary (A [21:0]). A [31:22] has a fixed value for a picture’s image. Check this condition for user-supplied framebuffer values and enforce it for driver-allocated buffers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
620 lines
14 KiB
C
620 lines
14 KiB
C
/*
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* Freescale i.MX Frame Buffer device driver
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*
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* Copyright (C) 2004 Sascha Hauer, Pengutronix
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* Based on acornfb.c Copyright (C) Russell King.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*
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* Please direct your questions and comments on this driver to the following
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* email address:
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*
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* linux-arm-kernel@lists.arm.linux.org.uk
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*/
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#include <common.h>
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#include <fb.h>
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#include <io.h>
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#include <mach/imxfb.h>
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#include <driver.h>
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#include <malloc.h>
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#include <errno.h>
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#include <init.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/sizes.h>
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#include <asm-generic/div64.h>
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#define LCDC_SSA 0x00
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#define LCDC_SIZE 0x04
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#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
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#ifdef CONFIG_ARCH_IMX1
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#define SIZE_YMAX(y) ((y) & 0x1ff)
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#else
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#define SIZE_YMAX(y) ((y) & 0x3ff)
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#endif
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#define LCDC_VPW 0x08
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#define VPW_VPW(x) ((x) & 0x3ff)
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#define LCDC_CPOS 0x0C
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#define CPOS_CC1 (1<<31)
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#define CPOS_CC0 (1<<30)
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#define CPOS_OP (1<<28)
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#define CPOS_CXP(x) (((x) & 3ff) << 16)
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#ifdef CONFIG_ARCH_IMX1
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#define CPOS_CYP(y) ((y) & 0x1ff)
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#else
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#define CPOS_CYP(y) ((y) & 0x3ff)
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#endif
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#define LCDC_LCWHB 0x10
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#define LCWHB_BK_EN (1<<31)
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#define LCWHB_CW(w) (((w) & 0x1f) << 24)
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#define LCWHB_CH(h) (((h) & 0x1f) << 16)
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#define LCWHB_BD(x) ((x) & 0xff)
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#define LCDC_LCHCC 0x14
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#ifdef CONFIG_ARCH_IMX1
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#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
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#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
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#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
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#else
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#define LCHCC_CUR_COL_R(r) (((r) & 0x3f) << 12)
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#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 6)
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#define LCHCC_CUR_COL_B(b) ((b) & 0x3f)
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#endif
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#define LCDC_PCR 0x18
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#define LCDC_HCR 0x1C
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#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
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#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
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#define HCR_H_WAIT_2(x) ((x) & 0xff)
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#define LCDC_VCR 0x20
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#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
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#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
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#define VCR_V_WAIT_2(x) ((x) & 0xff)
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#define LCDC_POS 0x24
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#define POS_POS(x) ((x) & 1f)
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#define LCDC_LSCR1 0x28
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/* bit fields in imxfb.h */
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#define LCDC_PWMR 0x2C
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/* bit fields in imxfb.h */
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#define LCDC_DMACR 0x30
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/* bit fields in imxfb.h */
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#define LCDC_RMCR 0x34
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#ifdef CONFIG_ARCH_IMX1
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#define RMCR_LCDC_EN (1<<1)
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#else
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#define RMCR_LCDC_EN 0
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#endif
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#define RMCR_SELF_REF (1<<0)
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#define LCDC_LCDICR 0x38
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#define LCDICR_INT_SYN (1<<2)
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#define LCDICR_INT_CON (1)
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#define LCDC_LCDISR 0x40
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#define LCDISR_UDR_ERR (1<<3)
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#define LCDISR_ERR_RES (1<<2)
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#define LCDISR_EOF (1<<1)
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#define LCDISR_BOF (1<<0)
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#define LCDC_LGWSAR 0x50
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#define LCDC_LGWSR 0x54
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#define LCDC_LGWVPWR 0x58
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#define LCDC_LGWPOR 0x5c
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#define LCDC_LGWPR 0x60
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#define LCDC_LGWCR 0x64
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#define LGWCR_GWAV(alpha) (((alpha) & 0xff) << 24)
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#define LGWCR_GWE (1 << 22)
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#define LCDC_LGWDCR 0x68
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/*
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* These are the bitfields for each
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* display depth that we support.
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*/
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struct imxfb_rgb {
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struct fb_bitfield red;
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struct fb_bitfield green;
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struct fb_bitfield blue;
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struct fb_bitfield transp;
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};
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struct imxfb_info {
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void __iomem *regs;
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struct clk *ahb_clk;
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struct clk *ipg_clk;
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struct clk *per_clk;
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u_int pcr;
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u_int pwmr;
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u_int lscr1;
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u_int dmacr;
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u_int cmap_inverse:1,
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cmap_static:1,
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unused:30;
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struct imx_fb_videomode *mode;
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struct fb_info info;
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struct device_d *dev;
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void (*enable)(int enable);
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unsigned int alpha;
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struct fb_info overlay;
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};
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#define IMX_NAME "IMX"
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/*
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* Minimum X and Y resolutions
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*/
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#define MIN_XRES 64
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#define MIN_YRES 64
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/* Actually this really is 18bit support, the lowest 2 bits of each colour
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* are unused in hardware. We claim to have 24bit support to make software
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* like X work, which does not support 18bit.
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*/
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static struct imxfb_rgb def_rgb_18 = {
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.red = {.offset = 16, .length = 8,},
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.green = {.offset = 8, .length = 8,},
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.blue = {.offset = 0, .length = 8,},
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.transp = {.offset = 0, .length = 0,},
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};
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static struct imxfb_rgb def_rgb_16_tft = {
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.red = {.offset = 11, .length = 5,},
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.green = {.offset = 5, .length = 6,},
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.blue = {.offset = 0, .length = 5,},
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.transp = {.offset = 0, .length = 0,},
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};
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static struct imxfb_rgb def_rgb_16_stn = {
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.red = {.offset = 8, .length = 4,},
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.green = {.offset = 4, .length = 4,},
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.blue = {.offset = 0, .length = 4,},
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.transp = {.offset = 0, .length = 0,},
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};
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static struct imxfb_rgb def_rgb_8 = {
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.red = {.offset = 0, .length = 8,},
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.green = {.offset = 0, .length = 8,},
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.blue = {.offset = 0, .length = 8,},
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.transp = {.offset = 0, .length = 0,},
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};
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static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
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{
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chan &= 0xffff;
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chan >>= 16 - bf->length;
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return chan << bf->offset;
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}
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static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
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u_int trans, struct fb_info *info)
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{
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struct imxfb_info *fbi = info->priv;
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int ret = 1;
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u32 val;
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/*
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* If inverse mode was selected, invert all the colours
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* rather than the register number. The register number
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* is what you poke into the framebuffer to produce the
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* colour you requested.
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*/
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if (fbi->cmap_inverse) {
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red = 0xffff - red;
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green = 0xffff - green;
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blue = 0xffff - blue;
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}
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/*
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* If greyscale is true, then we convert the RGB value
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* to greyscale no matter what visual we are using.
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*/
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if (info->grayscale)
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red = green = blue = (19595 * red + 38470 * green +
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7471 * blue) >> 16;
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#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
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if (regno < 256) {
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val = (CNVT_TOHW(red, 4) << 8) |
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(CNVT_TOHW(green,4) << 4) |
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CNVT_TOHW(blue, 4);
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writel(val, fbi->regs + 0x800 + (regno << 2));
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ret = 0;
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}
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return ret;
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}
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static void imxfb_enable_controller(struct fb_info *info)
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{
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struct imxfb_info *fbi = info->priv;
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writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR);
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clk_enable(fbi->ahb_clk);
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clk_enable(fbi->ipg_clk);
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clk_enable(fbi->per_clk);
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if (fbi->enable)
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fbi->enable(1);
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}
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static void imxfb_disable_controller(struct fb_info *info)
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{
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struct imxfb_info *fbi = info->priv;
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if (fbi->enable)
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fbi->enable(0);
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writel(0, fbi->regs + LCDC_RMCR);
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clk_disable(fbi->per_clk);
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clk_disable(fbi->ipg_clk);
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clk_disable(fbi->ahb_clk);
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}
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/*
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* imxfb_activate_var():
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* Configures LCD Controller based on entries in var parameter. Settings are
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* only written to the controller if changes were made.
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*/
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static int imxfb_activate_var(struct fb_info *info)
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{
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struct fb_videomode *mode = info->mode;
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struct imxfb_rgb *rgb;
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unsigned long lcd_clk;
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unsigned long long tmp;
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struct imxfb_info *fbi = info->priv;
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u32 pcr;
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int i;
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for (i = 0; i < info->modes.num_modes; i++) {
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if (!strcmp(fbi->mode[i].mode.name, mode->name)) {
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fbi->pcr = fbi->mode[i].pcr;
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break;
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}
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}
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/* physical screen start address */
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writel(VPW_VPW(mode->xres * info->bits_per_pixel / 8 / 4),
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fbi->regs + LCDC_VPW);
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writel(HCR_H_WIDTH(mode->hsync_len - 1) |
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HCR_H_WAIT_1(mode->right_margin - 1) |
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HCR_H_WAIT_2(mode->left_margin - 3),
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fbi->regs + LCDC_HCR);
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writel(VCR_V_WIDTH(mode->vsync_len) |
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VCR_V_WAIT_1(mode->lower_margin) |
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VCR_V_WAIT_2(mode->upper_margin),
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fbi->regs + LCDC_VCR);
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writel(SIZE_XMAX(info->xres) | SIZE_YMAX(info->yres),
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fbi->regs + LCDC_SIZE);
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writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
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writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
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writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
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writel((unsigned long)fbi->info.screen_base, fbi->regs + LCDC_SSA);
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/* panning offset 0 (0 pixel offset) */
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writel(0x0, fbi->regs + LCDC_POS);
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/* disable hardware cursor */
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writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1),
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fbi->regs + LCDC_CPOS);
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lcd_clk = clk_get_rate(fbi->per_clk);
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tmp = mode->pixclock * (unsigned long long)lcd_clk;
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do_div(tmp, 1000000);
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if (do_div(tmp, 1000000) > 500000)
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tmp++;
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pcr = (unsigned int)tmp;
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if (--pcr > 0x3f) {
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pcr = 0x3f;
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printk(KERN_WARNING "Must limit pixel clock to %luHz\n",
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lcd_clk / pcr);
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}
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switch (info->bits_per_pixel) {
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case 32:
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pcr |= PCR_BPIX_18;
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rgb = &def_rgb_18;
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break;
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case 16:
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default:
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#ifdef CONFIG_ARCH_IMX1
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pcr |= PCR_BPIX_12;
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#else
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pcr |= PCR_BPIX_16;
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#endif
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if (fbi->pcr & PCR_TFT)
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rgb = &def_rgb_16_tft;
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else
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rgb = &def_rgb_16_stn;
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break;
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case 8:
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pcr |= PCR_BPIX_8;
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rgb = &def_rgb_8;
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break;
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}
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writel(fbi->pcr | pcr, fbi->regs + LCDC_PCR);
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/*
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* Copy the RGB parameters for this display
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* from the machine specific parameters.
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*/
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info->red = rgb->red;
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info->green = rgb->green;
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info->blue = rgb->blue;
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info->transp = rgb->transp;
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return 0;
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}
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static struct fb_ops imxfb_ops = {
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.fb_setcolreg = imxfb_setcolreg,
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.fb_enable = imxfb_enable_controller,
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.fb_disable = imxfb_disable_controller,
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.fb_activate_var = imxfb_activate_var,
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};
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static int imxfb_allocate_fbbuffer(const struct device_d *dev,
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struct fb_info *info, void *forcefb)
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{
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size_t fbsize = info->xres * info->yres * (info->bits_per_pixel >> 3);
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/*
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* The buffer must be completely contained in an aligned 4 MiB memory
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* area.
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*/
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if (forcefb) {
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if (ALIGN((unsigned long)forcefb, SZ_4M) !=
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ALIGN((unsigned long)forcefb + fbsize, SZ_4M)) {
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dev_err(dev,
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"provided frame buffer crosses a 4 MiB boundary\n");
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return -EINVAL;
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}
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info->screen_base = forcefb;
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} else {
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/*
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* memalign implements a stricter condition on the memory
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* allocation as necessary, but in the absense of a better
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* function just use it.
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*/
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info->screen_base = memalign(fbsize, SZ_4M);
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if (!info->screen_base)
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return -ENOMEM;
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memset(info->screen_base, 0, fbsize);
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}
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return 0;
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}
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#ifdef CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY
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static void imxfb_overlay_enable_controller(struct fb_info *overlay)
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{
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struct imxfb_info *fbi = overlay->priv;
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unsigned int tmp;
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tmp = readl(fbi->regs + LCDC_LGWCR);
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tmp |= LGWCR_GWE;
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writel(tmp , fbi->regs + LCDC_LGWCR);
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}
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static void imxfb_overlay_disable_controller(struct fb_info *overlay)
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{
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struct imxfb_info *fbi = overlay->priv;
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unsigned int tmp;
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tmp = readl(fbi->regs + LCDC_LGWCR);
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tmp &= ~LGWCR_GWE;
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writel(tmp , fbi->regs + LCDC_LGWCR);
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}
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static int imxfb_overlay_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
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u_int trans, struct fb_info *info)
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{
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return 0;
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}
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static struct fb_ops imxfb_overlay_ops = {
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.fb_setcolreg = imxfb_overlay_setcolreg,
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.fb_enable = imxfb_overlay_enable_controller,
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.fb_disable = imxfb_overlay_disable_controller,
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};
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static int imxfb_alpha_set(struct param_d *param, void *priv)
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{
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struct fb_info *overlay = priv;
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struct imxfb_info *fbi = overlay->priv;
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unsigned int tmp;
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if (fbi->alpha > 0xff)
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fbi->alpha = 0xff;
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tmp = readl(fbi->regs + LCDC_LGWCR);
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tmp &= ~LGWCR_GWAV(0xff);
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tmp |= LGWCR_GWAV(fbi->alpha);
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writel(tmp , fbi->regs + LCDC_LGWCR);
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return 0;
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}
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static int imxfb_register_overlay(struct imxfb_info *fbi, void *fb)
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{
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struct fb_info *overlay;
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struct imxfb_rgb *rgb;
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int ret;
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overlay = &fbi->overlay;
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overlay->priv = fbi;
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overlay->mode = fbi->info.mode;
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overlay->xres = fbi->info.xres;
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overlay->yres = fbi->info.yres;
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overlay->bits_per_pixel = fbi->info.bits_per_pixel;
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overlay->fbops = &imxfb_overlay_ops;
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ret = imxfb_allocate_fbbuffer(fbi->dev, overlay, fb);
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if (ret < 0)
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return ret;
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writel((unsigned long)overlay->screen_base, fbi->regs + LCDC_LGWSAR);
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writel(SIZE_XMAX(overlay->xres) | SIZE_YMAX(overlay->yres),
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fbi->regs + LCDC_LGWSR);
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writel(VPW_VPW(overlay->xres * overlay->bits_per_pixel / 8 / 4),
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|
fbi->regs + LCDC_LGWVPWR);
|
|
writel(0, fbi->regs + LCDC_LGWPR);
|
|
writel(LGWCR_GWAV(0x0), fbi->regs + LCDC_LGWCR);
|
|
|
|
switch (overlay->bits_per_pixel) {
|
|
case 32:
|
|
rgb = &def_rgb_18;
|
|
break;
|
|
case 16:
|
|
default:
|
|
if (fbi->pcr & PCR_TFT)
|
|
rgb = &def_rgb_16_tft;
|
|
else
|
|
rgb = &def_rgb_16_stn;
|
|
break;
|
|
case 8:
|
|
rgb = &def_rgb_8;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Copy the RGB parameters for this display
|
|
* from the machine specific parameters.
|
|
*/
|
|
overlay->red = rgb->red;
|
|
overlay->green = rgb->green;
|
|
overlay->blue = rgb->blue;
|
|
overlay->transp = rgb->transp;
|
|
|
|
ret = register_framebuffer(overlay);
|
|
if (ret < 0) {
|
|
dev_err(fbi->dev, "failed to register framebuffer\n");
|
|
return ret;
|
|
}
|
|
|
|
dev_add_param_int(&overlay->dev, "alpha", imxfb_alpha_set,
|
|
NULL, &fbi->alpha, "%u", overlay);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static int imxfb_probe(struct device_d *dev)
|
|
{
|
|
struct imxfb_info *fbi;
|
|
struct fb_info *info;
|
|
struct imx_fb_platform_data *pdata = dev->platform_data;
|
|
struct fb_videomode *mode_list;
|
|
int ret, i;
|
|
|
|
if (!pdata)
|
|
return -ENODEV;
|
|
|
|
if (!pdata->num_modes) {
|
|
dev_err(dev, "no modes. bailing out\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
mode_list = xzalloc(sizeof(*mode_list) * pdata->num_modes);
|
|
for (i = 0; i < pdata->num_modes; i++)
|
|
mode_list[i] = pdata->mode[i].mode;
|
|
|
|
fbi = xzalloc(sizeof(*fbi));
|
|
info = &fbi->info;
|
|
|
|
fbi->per_clk = clk_get(dev, "per");
|
|
if (IS_ERR(fbi->per_clk))
|
|
return PTR_ERR(fbi->per_clk);
|
|
|
|
fbi->ahb_clk = clk_get(dev, "ahb");
|
|
if (IS_ERR(fbi->ahb_clk))
|
|
return PTR_ERR(fbi->ahb_clk);
|
|
|
|
fbi->ipg_clk = clk_get(dev, "ipg");
|
|
if (IS_ERR(fbi->ipg_clk))
|
|
return PTR_ERR(fbi->ipg_clk);
|
|
|
|
fbi->mode = pdata->mode;
|
|
fbi->regs = dev_request_mem_region(dev, 0);
|
|
if (IS_ERR(fbi->regs))
|
|
return PTR_ERR(fbi->regs);
|
|
|
|
fbi->pcr = pdata->mode->pcr;
|
|
fbi->pwmr = pdata->pwmr;
|
|
fbi->lscr1 = pdata->lscr1;
|
|
fbi->dmacr = pdata->dmacr;
|
|
fbi->enable = pdata->enable;
|
|
fbi->dev = dev;
|
|
info->priv = fbi;
|
|
info->modes.modes = mode_list;
|
|
info->modes.num_modes = pdata->num_modes;
|
|
info->mode = &pdata->mode->mode;
|
|
info->xres = pdata->mode->mode.xres;
|
|
info->yres = pdata->mode->mode.yres;
|
|
info->bits_per_pixel = pdata->mode->bpp;
|
|
info->fbops = &imxfb_ops;
|
|
|
|
dev_info(dev, "i.MX Framebuffer driver\n");
|
|
|
|
|
|
ret = imxfb_allocate_fbbuffer(dev, info, pdata->framebuffer);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
imxfb_activate_var(&fbi->info);
|
|
|
|
ret = register_framebuffer(&fbi->info);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to register framebuffer\n");
|
|
return ret;
|
|
}
|
|
#ifdef CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY
|
|
imxfb_register_overlay(fbi, pdata->framebuffer_ovl);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static struct driver_d imxfb_driver = {
|
|
.name = "imxfb",
|
|
.probe = imxfb_probe,
|
|
};
|
|
device_platform_driver(imxfb_driver);
|