This better separates the DMA from the MMU functionality. Also move all drivers that only depends on asm/mmu.h for the alloc functions over to the common header. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
548 lines
14 KiB
C
548 lines
14 KiB
C
/*
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* Copyright (C) 2010 Marc Kleine-Budde, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Derived from the linux-2.6 pxa framebuffer driver:
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*
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* Copyright (C) 1999 Eric A. Thomas.
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* Copyright (C) 2004 Jean-Frederic Clere.
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* Copyright (C) 2004 Ian Campbell.
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* Copyright (C) 2004 Jeff Lackey.
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* Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
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* which in turn is:
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* Based on acornfb.c Copyright (C) Russell King.
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*
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*/
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#include <common.h>
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#include <dma.h>
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#include <driver.h>
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#include <errno.h>
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#include <fb.h>
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#include <init.h>
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#include <malloc.h>
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#include <linux/err.h>
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#include <mach/clock.h>
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#include <mach/pxa-regs.h>
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#include <mach/regs-lcd.h>
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#include <mach/pxafb.h>
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#include <asm/io.h>
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#include <asm-generic/div64.h>
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/* PXA LCD DMA descriptor */
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struct pxafb_dma_descriptor {
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unsigned int fdadr;
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unsigned int fsadr;
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unsigned int fidr;
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unsigned int ldcmd;
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};
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enum {
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PAL_NONE = -1,
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PAL_BASE = 0,
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PAL_MAX,
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};
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enum {
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DMA_BASE = 0,
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DMA_UPPER = 0,
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DMA_LOWER = 1,
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DMA_MAX,
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};
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struct pxafb_dma_buff {
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struct pxafb_dma_descriptor dma_desc[DMA_MAX * 2];
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};
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struct pxafb_info {
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void __iomem *regs;
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struct pxafb_dma_buff *dma_buff;
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dma_addr_t fdadr[DMA_MAX * 2];
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u32 lccr0;
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u32 lccr3;
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u32 lccr4;
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u32 reg_lccr0;
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u32 reg_lccr1;
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u32 reg_lccr2;
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u32 reg_lccr3;
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u32 reg_lccr4;
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struct pxafb_videomode *mode;
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struct fb_info info;
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struct device_d *dev;
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void (*lcd_power)(int);
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void (*backlight_power)(int);
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};
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#define info_to_pxafb_info(_info) container_of(_info, struct pxafb_info, info)
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static inline unsigned long
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lcd_readl(struct pxafb_info *fbi, unsigned int off)
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{
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return __raw_readl(fbi->regs + off);
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}
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static inline void
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lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
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{
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__raw_writel(val, fbi->regs + off);
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}
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static inline void pxafb_backlight_power(struct pxafb_info *fbi, int on)
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{
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pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
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if (fbi->backlight_power)
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fbi->backlight_power(on);
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}
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static inline void pxafb_lcd_power(struct pxafb_info *fbi, int on)
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{
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pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
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if (fbi->lcd_power)
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fbi->lcd_power(on);
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}
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static void pxafb_enable_controller(struct fb_info *info)
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{
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struct pxafb_info *fbi = info_to_pxafb_info(info);
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pr_debug("pxafb: Enabling LCD controller\n");
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pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
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pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
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pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
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pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
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pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
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pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
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pr_debug("dma_desc 0x%08x\n", (unsigned int) &fbi->dma_buff->dma_desc[DMA_BASE]);
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/* enable LCD controller clock */
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CKEN |= CKEN_LCD;
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if (fbi->lccr0 & LCCR0_LCDT)
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return;
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/* Sequence from 11.7.10 */
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lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
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lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
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lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
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lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
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lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
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lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
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lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
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lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
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pxafb_lcd_power(fbi, 1);
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pxafb_backlight_power(fbi, 1);
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}
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static void pxafb_disable_controller(struct fb_info *info)
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{
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struct pxafb_info *fbi = info_to_pxafb_info(info);
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u32 lccr0;
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pxafb_backlight_power(fbi, 0);
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pxafb_lcd_power(fbi, 0);
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/* Clear LCD Status Register */
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lcd_writel(fbi, LCSR, 0xffffffff);
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lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
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lcd_writel(fbi, LCCR0, lccr0);
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lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
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/* disable LCD controller clock */
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CKEN &= ~CKEN_LCD;
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}
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static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
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unsigned long start, size_t size)
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{
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struct pxafb_dma_descriptor *dma_desc;
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if (dma < 0 || dma >= DMA_MAX * 2)
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return -EINVAL;
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dma_desc = &fbi->dma_buff->dma_desc[dma];
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dma_desc->fsadr = start;
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dma_desc->fidr = 0;
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dma_desc->ldcmd = size;
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if (pal < 0 || pal >= PAL_MAX * 2) {
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dma_desc->fdadr = virt_to_phys(dma_desc);
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fbi->fdadr[dma] = virt_to_phys(dma_desc);
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} else {
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#if 0
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struct pxafb_dma_descriptor *pal_desc;
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pal_desc = &fbi->dma_buff->pal_desc[pal];
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pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
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pal_desc->fidr = 0;
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if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
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pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
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else
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pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
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pal_desc->ldcmd |= LDCMD_PAL;
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/* flip back and forth between palette and frame buffer */
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pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
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dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
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fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
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#endif
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}
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return 0;
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}
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static void setup_base_frame(struct pxafb_info *fbi)
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{
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struct pxafb_videomode *mode = fbi->mode;
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struct fb_info *info = &fbi->info;
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int nbytes, dma, pal, bpp = info->bits_per_pixel;
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unsigned long line_length, offset;
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dma = DMA_BASE;
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pal = (bpp >= 16) ? PAL_NONE : PAL_BASE;
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line_length = info->xres * info->bits_per_pixel / 8;
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nbytes = line_length * mode->mode.yres;
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offset = virt_to_phys(info->screen_base);
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if (fbi->lccr0 & LCCR0_SDS) {
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nbytes = nbytes / 2;
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setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
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}
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setup_frame_dma(fbi, dma, pal, offset, nbytes);
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}
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/*
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* Calculate the PCD value from the clock rate (in picoseconds).
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* We take account of the PPCR clock setting.
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* From PXA Developer's Manual:
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*
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* PixelClock = LCLK
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* -------------
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* 2 ( PCD + 1 )
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*
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* PCD = LCLK
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* ------------- - 1
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* 2(PixelClock)
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*
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* Where:
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* LCLK = LCD/Memory Clock
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* PCD = LCCR3[7:0]
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*
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* PixelClock here is in Hz while the pixclock argument given is the
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* period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
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*
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* The function get_lclk_frequency_10khz returns LCLK in units of
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* 10khz. Calling the result of this function lclk gives us the
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* following
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*
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* PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
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* -------------------------------------- - 1
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* 2
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*
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* Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
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*/
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static inline unsigned int get_pcd(struct pxafb_info *fbi,
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unsigned int pixclock)
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{
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unsigned long long pcd;
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/*
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* FIXME: Need to take into account Double Pixel Clock mode
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* (DPC) bit? or perhaps set it based on the various clock
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* speeds
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*/
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pcd = (unsigned long long)(pxa_get_lcdclk() / 10000);
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pcd *= pixclock;
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do_div(pcd, 100000000 * 2);
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/* no need for this, since we should subtract 1 anyway. they cancel */
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/* pcd += 1; */ /* make up for integer math truncations */
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return (unsigned int)pcd;
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}
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static void setup_parallel_timing(struct pxafb_info *fbi)
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{
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struct fb_info *info = &fbi->info;
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struct fb_videomode *mode = info->mode;
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unsigned int lines_per_panel, pcd = get_pcd(fbi, mode->pixclock);
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fbi->reg_lccr1 =
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LCCR1_DisWdth(mode->xres) +
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LCCR1_HorSnchWdth(mode->hsync_len) +
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LCCR1_BegLnDel(mode->left_margin) +
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LCCR1_EndLnDel(mode->right_margin);
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/*
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* If we have a dual scan LCD, we need to halve
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* the YRES parameter.
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*/
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lines_per_panel = mode->yres;
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if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
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lines_per_panel /= 2;
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fbi->reg_lccr2 =
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LCCR2_DisHght(lines_per_panel) +
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LCCR2_VrtSnchWdth(mode->vsync_len) +
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LCCR2_BegFrmDel(mode->upper_margin) +
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LCCR2_EndFrmDel(mode->lower_margin);
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fbi->reg_lccr3 = fbi->lccr3 |
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(mode->sync & FB_SYNC_HOR_HIGH_ACT ?
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LCCR3_HorSnchH : LCCR3_HorSnchL) |
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(mode->sync & FB_SYNC_VERT_HIGH_ACT ?
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LCCR3_VrtSnchH : LCCR3_VrtSnchL);
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if (pcd)
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fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
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}
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/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
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static inline int var_to_depth(struct fb_info *info)
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{
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return info->red.length + info->green.length +
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info->blue.length + info->transp.length;
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}
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/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
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static int pxafb_var_to_bpp(struct fb_info *info)
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{
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int bpp = -EINVAL;
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switch (info->bits_per_pixel) {
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case 1: bpp = 0; break;
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case 2: bpp = 1; break;
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case 4: bpp = 2; break;
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case 8: bpp = 3; break;
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case 16: bpp = 4; break;
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case 24:
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switch (var_to_depth(info)) {
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case 18: bpp = 6; break; /* 18-bits/pixel packed */
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case 19: bpp = 8; break; /* 19-bits/pixel packed */
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case 24: bpp = 9; break;
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}
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break;
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case 32:
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switch (var_to_depth(info)) {
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case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
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case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
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case 25: bpp = 10; break;
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}
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break;
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}
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return bpp;
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}
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/*
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* pxafb_var_to_lccr3():
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* Convert a bits per pixel value to the correct bit pattern for LCCR3
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*
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* NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
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* implication of the acutal use of transparency bit, which we handle it
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* here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
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* Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
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*
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* Transparency for palette pixel formats is not supported at the moment.
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*/
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static uint32_t pxafb_var_to_lccr3(struct fb_info *info)
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{
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int bpp = pxafb_var_to_bpp(info);
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uint32_t lccr3;
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if (bpp < 0)
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return 0;
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lccr3 = LCCR3_BPP(bpp);
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switch (var_to_depth(info)) {
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case 16: lccr3 |= info->transp.length ? LCCR3_PDFOR_3 : 0; break;
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case 18: lccr3 |= LCCR3_PDFOR_3; break;
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case 24: lccr3 |= info->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
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break;
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case 19:
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case 25: lccr3 |= LCCR3_PDFOR_0; break;
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}
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return lccr3;
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}
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/*
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* Configures LCD Controller based on entries in fbi parameter.
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*/
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static int pxafb_activate_var(struct pxafb_info *fbi)
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{
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struct fb_info *info = &fbi->info;
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setup_parallel_timing(fbi);
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setup_base_frame(fbi);
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fbi->reg_lccr0 = fbi->lccr0 |
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(LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
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LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
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fbi->reg_lccr3 |= pxafb_var_to_lccr3(info);
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fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
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fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
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return 0;
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}
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#define SET_PIXFMT(v, r, g, b) \
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({ \
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(v)->blue.length = (b); (v)->blue.offset = 0; \
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(v)->green.length = (g); (v)->green.offset = (b); \
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(v)->red.length = (r); (v)->red.offset = (b) + (g); \
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})
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/*
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* set the RGBT bitfields of fb_var_screeninf according to
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* var->bits_per_pixel and given depth
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*/
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static void pxafb_set_pixfmt(struct fb_info *info)
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{
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if (info->bits_per_pixel < 16) {
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/* indexed pixel formats */
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info->red.offset = 0; info->red.length = 8;
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info->green.offset = 0; info->green.length = 8;
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info->blue.offset = 0; info->blue.length = 8;
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info->transp.offset = 0; info->transp.length = 8;
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}
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switch (info->bits_per_pixel) {
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case 16: SET_PIXFMT(info, 5, 6, 5); break; /* RGB565 */
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case 18: SET_PIXFMT(info, 6, 6, 6); break; /* RGB666 */
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case 24: SET_PIXFMT(info, 8, 8, 8); break; /* RGB888 */
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}
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}
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static void pxafb_decode_mach_info(struct pxafb_info *fbi,
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struct pxafb_platform_data *inf)
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{
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unsigned int lcd_conn = inf->lcd_conn;
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switch (lcd_conn & LCD_TYPE_MASK) {
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case LCD_TYPE_MONO_STN:
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fbi->lccr0 = LCCR0_CMS;
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break;
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case LCD_TYPE_MONO_DSTN:
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fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
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break;
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case LCD_TYPE_COLOR_STN:
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fbi->lccr0 = 0;
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break;
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case LCD_TYPE_COLOR_DSTN:
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fbi->lccr0 = LCCR0_SDS;
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break;
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case LCD_TYPE_COLOR_TFT:
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fbi->lccr0 = LCCR0_PAS;
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break;
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case LCD_TYPE_SMART_PANEL:
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fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
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break;
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}
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if (lcd_conn == LCD_MONO_STN_8BPP)
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fbi->lccr0 |= LCCR0_DPD;
|
|
|
|
fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
|
|
|
|
fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff) |
|
|
(lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0 |
|
|
(lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
|
|
|
|
pxafb_set_pixfmt(&fbi->info);
|
|
}
|
|
|
|
static struct fb_ops pxafb_ops = {
|
|
.fb_enable = pxafb_enable_controller,
|
|
.fb_disable = pxafb_disable_controller,
|
|
};
|
|
|
|
static int pxafb_probe(struct device_d *dev)
|
|
{
|
|
struct pxafb_platform_data *pdata = dev->platform_data;
|
|
struct pxafb_info *fbi;
|
|
struct fb_info *info;
|
|
int ret;
|
|
|
|
if (!pdata)
|
|
return -ENODEV;
|
|
|
|
fbi = xzalloc(sizeof(*fbi));
|
|
info = &fbi->info;
|
|
|
|
fbi->mode = pdata->mode;
|
|
fbi->regs = dev_request_mem_region(dev, 0);
|
|
if (IS_ERR(fbi->regs))
|
|
return PTR_ERR(fbi->regs);
|
|
|
|
fbi->dev = dev;
|
|
fbi->lcd_power = pdata->lcd_power;
|
|
fbi->backlight_power = pdata->backlight_power;
|
|
info->mode = &pdata->mode->mode;
|
|
info->fbops = &pxafb_ops;
|
|
|
|
info->xres = pdata->mode->mode.xres;
|
|
info->yres = pdata->mode->mode.yres;
|
|
info->bits_per_pixel = pdata->mode->bpp;
|
|
|
|
pxafb_decode_mach_info(fbi, pdata);
|
|
|
|
dev_info(dev, "PXA Framebuffer driver\n");
|
|
|
|
if (pdata->framebuffer)
|
|
fbi->info.screen_base = pdata->framebuffer;
|
|
else
|
|
fbi->info.screen_base =
|
|
PTR_ALIGN(dma_alloc_coherent(info->xres * info->yres *
|
|
(info->bits_per_pixel >> 3) + PAGE_SIZE,
|
|
DMA_ADDRESS_BROKEN),
|
|
PAGE_SIZE);
|
|
|
|
fbi->dma_buff = PTR_ALIGN(dma_alloc_coherent(sizeof(struct pxafb_dma_buff) + 16,
|
|
DMA_ADDRESS_BROKEN), 16);
|
|
|
|
pxafb_activate_var(fbi);
|
|
|
|
ret = register_framebuffer(&fbi->info);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to register framebuffer\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct driver_d pxafb_driver = {
|
|
.name = "pxafb",
|
|
.probe = pxafb_probe,
|
|
};
|
|
device_platform_driver(pxafb_driver);
|