163 lines
4.1 KiB
C
163 lines
4.1 KiB
C
#include <init.h>
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#include <sizes.h>
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#include <io.h>
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#include <debug_ll.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <mach/am33xx-silicon.h>
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#include <mach/am33xx-clock.h>
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#include <mach/generic.h>
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#include <mach/sdrc.h>
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#include <mach/sys_info.h>
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#include <mach/syslib.h>
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#include <mach/am33xx-mux.h>
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#include <mach/am33xx-generic.h>
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#include <mach/wdt.h>
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#include "beaglebone.h"
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#define DDR2_RD_DQS 0x12
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#define DDR2_PHY_FIFO_WE 0x80
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#define DDR2_WR_DQS 0x00
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#define DDR2_PHY_WRLVL 0x00
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#define DDR2_PHY_GATELVL 0x00
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#define DDR2_PHY_WR_DATA 0x40
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static const struct am33xx_cmd_control ddr2_cmd_ctrl = {
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.slave_ratio0 = 0x80,
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.dll_lock_diff0 = 0x0,
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.invert_clkout0 = 0x0,
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.slave_ratio1 = 0x80,
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.dll_lock_diff1 = 0x0,
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.invert_clkout1 = 0x0,
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.slave_ratio2 = 0x80,
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.dll_lock_diff2 = 0x0,
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.invert_clkout2 = 0x0,
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};
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static const struct am33xx_emif_regs ddr2_regs = {
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.emif_read_latency = 0x100005,
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.emif_tim1 = 0x0666B3C9,
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.emif_tim2 = 0x243631CA,
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.emif_tim3 = 0x0000033F,
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.sdram_config = 0x41805332,
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.sdram_config2 = 0x41805332,
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.sdram_ref_ctrl = 0x0000081A,
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};
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static const struct am33xx_ddr_data ddr2_data = {
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.rd_slave_ratio0 = (DDR2_RD_DQS << 30) | (DDR2_RD_DQS << 20) |
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(DDR2_RD_DQS << 10) | (DDR2_RD_DQS << 0),
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.wr_dqs_slave_ratio0 = (DDR2_WR_DQS << 30) | (DDR2_WR_DQS << 20) |
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(DDR2_WR_DQS << 10) | (DDR2_WR_DQS << 0),
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.wrlvl_init_ratio0 = (DDR2_PHY_WRLVL << 30) |
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(DDR2_PHY_WRLVL << 20) |
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(DDR2_PHY_WRLVL << 10) |
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(DDR2_PHY_WRLVL << 0),
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.gatelvl_init_ratio0 = (DDR2_PHY_GATELVL << 30) |
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(DDR2_PHY_GATELVL << 20) |
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(DDR2_PHY_GATELVL << 10) |
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(DDR2_PHY_GATELVL << 0),
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.fifo_we_slave_ratio0 = (DDR2_PHY_FIFO_WE << 30) |
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(DDR2_PHY_FIFO_WE << 20) |
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(DDR2_PHY_FIFO_WE << 10) |
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(DDR2_PHY_FIFO_WE << 0),
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.wr_slave_ratio0 = (DDR2_PHY_WR_DATA << 30) |
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(DDR2_PHY_WR_DATA << 20) |
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(DDR2_PHY_WR_DATA << 10) |
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(DDR2_PHY_WR_DATA << 0),
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.use_rank0_delay = 0x01,
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.dll_lock_diff0 = 0x0,
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};
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static const struct am33xx_ddr_data ddr3_data = {
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.rd_slave_ratio0 = 0x38,
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.wr_dqs_slave_ratio0 = 0x44,
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.fifo_we_slave_ratio0 = 0x94,
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.wr_slave_ratio0 = 0x7D,
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.use_rank0_delay = 0x01,
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.dll_lock_diff0 = 0x0,
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};
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static const struct am33xx_cmd_control ddr3_cmd_ctrl = {
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.slave_ratio0 = 0x80,
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.dll_lock_diff0 = 0x1,
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.invert_clkout0 = 0x0,
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.slave_ratio1 = 0x80,
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.dll_lock_diff1 = 0x1,
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.invert_clkout1 = 0x0,
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.slave_ratio2 = 0x80,
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.dll_lock_diff2 = 0x1,
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.invert_clkout2 = 0x0,
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};
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static const struct am33xx_emif_regs ddr3_regs = {
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.emif_read_latency = 0x100007,
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.emif_tim1 = 0x0AAAD4DB,
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.emif_tim2 = 0x266B7FDA,
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.emif_tim3 = 0x501F867F,
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.zq_config = 0x50074BE4,
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.sdram_config = 0x61C05332,
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.sdram_config2 = 0x0,
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.sdram_ref_ctrl = 0xC30,
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};
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/**
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* @brief The basic entry point for board initialization.
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*
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* This is called as part of machine init (after arch init).
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* This is again called with stack in SRAM, so not too many
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* constructs possible here.
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*
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* @return void
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*/
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static int beaglebone_board_init(void)
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{
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/* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
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while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
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while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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if (am33xx_running_in_sdram())
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return 0;
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/* Setup the PLLs and the clocks for the peripherals */
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if (is_beaglebone_black()) {
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am33xx_pll_init(MPUPLL_M_500, 24, DDRPLL_M_400);
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am335x_sdram_init(0x18B, &ddr3_cmd_ctrl, &ddr3_regs,
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&ddr3_data);
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} else {
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am33xx_pll_init(MPUPLL_M_500, 24, DDRPLL_M_266);
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am335x_sdram_init(0x18B, &ddr2_cmd_ctrl, &ddr2_regs,
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&ddr2_data);
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}
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am33xx_uart0_soft_reset();
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am33xx_enable_uart0_pin_mux();
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omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
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putc_ll('>');
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return 0;
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}
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void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
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{
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unsigned sdram;
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am33xx_save_bootinfo(data);
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arm_cpu_lowlevel_init();
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beaglebone_board_init();
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if (is_beaglebone_black())
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sdram = SZ_512M;
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else
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sdram = SZ_256M;
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barebox_arm_entry(0x80000000, sdram, 0);
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}
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