116 lines
3.2 KiB
C
116 lines
3.2 KiB
C
/*
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* For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
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* Applications Processor Reference Manual, Rev. 0.2".
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <config.h>
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#include <asm/barebox-arm.h>
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#include <asm/barebox-arm-head.h>
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#include <mach/imx27-regs.h>
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#include <mach/imx-pll.h>
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#include <mach/esdctl.h>
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#include <mach/imx-nand.h>
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#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
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static void sdram_init(void)
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{
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int i;
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/*
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* DDR on CSD0
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*/
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/* Enable DDR SDRAM operation */
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writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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/* Set the driving strength */
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writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3));
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writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5));
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writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6));
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writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7));
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writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8));
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/* Initial reset */
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writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
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/* precharge CSD0 all banks */
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writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
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MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writel(0x00000000, 0xa0000f00); /* CSD0 precharge address (A10 = 1) */
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writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
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MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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for (i = 0; i < 8; i++)
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writel(0, 0xa0000f00);
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writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
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MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writeb(0xda, 0xa0000033);
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writeb(0xff, 0xa1000000);
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writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
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ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
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MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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}
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void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
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{
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unsigned long r;
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arm_cpu_lowlevel_init();
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/* ahb lite ip interface */
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writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0);
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writel(0xdffbfcfb, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1);
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writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0);
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writel(0xffffffff, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1);
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/* Skip SDRAM initialization if we run from RAM */
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r = get_pc();
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if (r > 0xa0000000 && r < 0xc0000000)
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imx27_barebox_entry(fdt);
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/* 399 MHz */
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writel(IMX_PLL_PD(0) |
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IMX_PLL_MFD(51) |
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IMX_PLL_MFI(7) |
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IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0);
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/* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
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writel(IMX_PLL_PD(1) |
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IMX_PLL_MFD(12) |
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IMX_PLL_MFI(9) |
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IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0);
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writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART |
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MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL |
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MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN |
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MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) |
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MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) |
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MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL |
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MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL |
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MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR);
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sdram_init();
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imx27_barebox_boot_nand_external(fdt);
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}
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extern char __dtb_imx27_phytec_phycard_s_rdk_bb_start[];
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ENTRY_FUNCTION(start_phytec_phycard_imx27, r0, r1, r2)
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{
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void *fdt;
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arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12);
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fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start - get_runtime_offset();
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phytec_phycard_imx27_common_init(fdt);
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}
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