430 lines
15 KiB
C
430 lines
15 KiB
C
/*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <linux/clk.h>
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#include <io.h>
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#include <of.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <mach/imx51-regs.h>
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#include <mach/imx53-regs.h>
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#include <dt-bindings/clock/imx5-clock.h>
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#include "clk.h"
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/* Register addresses of CCM*/
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#define CCM_CCR 0x00
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#define CCM_CCDR 0x04
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#define CCM_CSR 0x08
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#define CCM_CCSR 0x0C
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#define CCM_CACRR 0x10
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#define CCM_CBCDR 0x14
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#define CCM_CBCMR 0x18
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#define CCM_CSCMR1 0x1C
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#define CCM_CSCMR2 0x20
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#define CCM_CSCDR1 0x24
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#define CCM_CS1CDR 0x28
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#define CCM_CS2CDR 0x2C
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#define CCM_CDCDR 0x30
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#define CCM_CHSCDR 0x34
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#define CCM_CSCDR2 0x38
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#define CCM_CSCDR3 0x3C
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#define CCM_CSCDR4 0x40
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#define CCM_CWDR 0x44
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#define CCM_CDHIPR 0x48
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#define CCM_CDCR 0x4C
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#define CCM_CTOR 0x50
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#define CCM_CLPCR 0x54
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#define CCM_CISR 0x58
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#define CCM_CIMR 0x5C
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#define CCM_CCOSR 0x60
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#define CCM_CGPR 0x64
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#define CCM_CCGR0 0x68
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#define CCM_CCGR1 0x6C
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#define CCM_CCGR2 0x70
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#define CCM_CCGR3 0x74
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#define CCM_CCGR4 0x78
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#define CCM_CCGR5 0x7C
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#define CCM_CCGR6 0x80
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#define CCM_CCGR7 0x84
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#define CCM_CMEOR 0x84
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static struct clk *clks[IMX5_CLK_END];
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/* This is used multiple times */
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static const char *standard_pll_sel[] = {
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"pll1_sw",
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"pll2_sw",
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"pll3_sw",
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"lp_apm",
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};
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static const char *lp_apm_sel[] = {
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"osc",
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};
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static const char *periph_apm_sel[] = {
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"pll1_sw",
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"pll3_sw",
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"lp_apm",
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};
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static const char *main_bus_sel[] = {
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"pll2_sw",
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"periph_apm",
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};
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static const char *per_lp_apm_sel[] = {
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"main_bus",
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"lp_apm",
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};
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static const char *per_root_sel[] = {
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"per_podf",
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"ipg",
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};
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static const char *esdhc_c_sel[] = {
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"esdhc_a_podf",
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"esdhc_b_podf",
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};
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static const char *esdhc_d_sel[] = {
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"esdhc_a_podf",
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"esdhc_b_podf",
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};
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static const char *emi_slow_sel[] = {
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"main_bus",
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"ahb",
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};
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static const char *usb_phy_sel_str[] = {
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"osc",
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"usb_phy_podf",
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};
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static const char *mx51_ipu_di0_sel[] = {
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"di_pred",
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"osc",
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"ckih1",
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"tve_di",
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};
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static const char *mx53_ipu_di0_sel[] = {
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"di_pred",
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"osc",
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"ckih1",
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"di_pll4_podf",
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"dummy",
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"ldb_di0_div",
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};
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static const char *mx53_ldb_di0_sel[] = {
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"pll3_sw",
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"pll4_sw",
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};
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static const char *mx51_ipu_di1_sel[] = {
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"di_pred",
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"osc",
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"ckih1",
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"tve_di",
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"ipp_di1",
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};
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static const char *mx53_ipu_di1_sel[] = {
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"di_pred",
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"osc",
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"ckih1",
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"tve_di",
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"ipp_di1",
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"ldb_di1_div",
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};
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static const char *mx53_ldb_di1_sel[] = {
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"pll3_sw",
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"pll4_sw",
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};
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static const char *mx51_tve_ext_sel[] = {
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"osc",
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"ckih1",
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};
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static const char *mx53_tve_ext_sel[] = {
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"pll4_sw",
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"ckih1",
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};
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static const char *mx51_tve_sel[] = {
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"tve_pred",
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"tve_ext_sel",
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};
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static const char *ipu_sel[] = {
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"axi_a",
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"axi_b",
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"emi_slow_gate",
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"ahb",
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};
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static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate_ckil,
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unsigned long rate_osc, unsigned long rate_ckih1,
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unsigned long rate_ckih2)
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{
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writel(0xffffffff, base + CCM_CCGR0);
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writel(0xffffffff, base + CCM_CCGR1);
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writel(0xffffffff, base + CCM_CCGR2);
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writel(0xffffffff, base + CCM_CCGR3);
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writel(0xffffffff, base + CCM_CCGR4);
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writel(0xffffffff, base + CCM_CCGR5);
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writel(0xffffffff, base + CCM_CCGR6);
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writel(0xffffffff, base + CCM_CCGR7);
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clks[IMX5_CLK_DUMMY] = clk_fixed("dummy", 0);
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clks[IMX5_CLK_CKIL] = clk_fixed("ckil", rate_ckil);
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clks[IMX5_CLK_OSC] = clk_fixed("osc", rate_osc);
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clks[IMX5_CLK_CKIH1] = clk_fixed("ckih1", rate_ckih1);
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clks[IMX5_CLK_CKIH2] = clk_fixed("ckih2", rate_ckih2);
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clks[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", base + CCM_CCSR, 9, 1,
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lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
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clks[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", base + CCM_CBCMR, 12, 2,
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periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
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clks[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", base + CCM_CBCDR, 25, 1,
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main_bus_sel, ARRAY_SIZE(main_bus_sel));
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clks[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", base + CCM_CBCMR, 1, 1,
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per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
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clks[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", base + CCM_CBCDR, 6, 2);
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clks[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", base + CCM_CBCDR, 3, 3);
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clks[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", base + CCM_CBCDR, 0, 3);
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clks[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", base + CCM_CBCMR, 0, 1,
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per_root_sel, ARRAY_SIZE(per_root_sel));
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clks[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", base + CCM_CBCDR, 10, 3);
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clks[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + CCM_CBCDR, 8, 2);
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clks[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", base + CCM_CBCDR, 16, 3);
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clks[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", base + CCM_CBCDR, 19, 3);
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clks[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + CCM_CSCMR1, 24, 2,
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standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
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clks[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", base + CCM_CSCDR1, 3, 3);
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clks[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", base + CCM_CSCDR1, 0, 3);
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clks[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", base + CCM_CSCMR1, 20, 2,
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standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
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clks[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", base + CCM_CSCMR1, 16, 2,
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standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
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clks[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", base + CCM_CSCDR1, 16, 3);
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clks[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", base + CCM_CSCDR1, 11, 3);
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clks[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", base + CCM_CSCDR1, 22, 3);
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clks[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", base + CCM_CSCDR1, 19, 3);
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clks[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", base + CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
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clks[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", base + CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
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clks[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", base + CCM_CBCDR, 26, 1,
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emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
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clks[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", base + CCM_CBCDR, 22, 3);
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clks[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", base + CCM_CBCDR, 13, 3);
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clks[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + CCM_CSCMR1, 4, 2,
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standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
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clks[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", base + CCM_CSCDR2, 25, 3);
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clks[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", base + CCM_CSCDR2, 19, 6);
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clks[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", base + CCM_CSCMR1, 22, 2,
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standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
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clks[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", base + CCM_CSCDR1, 8, 3);
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clks[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", base + CCM_CSCDR1, 6, 2);
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clks[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", base + CCM_CDCDR, 3, 3);
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clks[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", base + CCM_CDCDR, 0, 3);
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clks[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", base + CCM_CSCMR1, 26, 1,
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usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
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clks[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", base + CCM_CACRR, 0, 3);
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}
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static void mx5_clocks_ipu_init(void __iomem *regs)
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{
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clks[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", regs + CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
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}
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static void mx51_clocks_ipu_init(void __iomem *regs)
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{
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clks[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_p("ipu_di0_sel", regs + CCM_CSCMR2, 26, 3,
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mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
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clks[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_p("ipu_di1_sel", regs + CCM_CSCMR2, 29, 3,
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mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
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clks[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_p("tve_ext_sel", regs + CCM_CSCMR1, 6, 1,
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mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel));
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clks[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", regs + CCM_CSCMR1, 7, 1,
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mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
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clks[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", regs + CCM_CDCDR, 28, 3);
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mx5_clocks_ipu_init(regs);
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clkdev_add_physbase(clks[IMX5_CLK_IPU_SEL], MX51_IPU_BASE_ADDR, "bus");
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clkdev_add_physbase(clks[IMX5_CLK_IPU_DI0_SEL], MX51_IPU_BASE_ADDR, "di0");
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clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX51_IPU_BASE_ADDR, "di1");
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}
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int __init mx51_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
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unsigned long rate_ckih1, unsigned long rate_ckih2)
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{
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clks[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX51_PLL1_BASE_ADDR);
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clks[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX51_PLL2_BASE_ADDR);
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clks[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX51_PLL3_BASE_ADDR);
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mx5_clocks_common_init(regs, rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
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clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART3_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_I2C1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_I2C2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_GPT1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_IPG], MX51_CSPI_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_ECSPI_PODF], MX51_ECSPI1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_ECSPI_PODF], MX51_ECSPI2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_IPG], MX51_MXC_FEC_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_ESDHC_A_PODF], MX51_MMC_SDHC1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_ESDHC_B_PODF], MX51_MMC_SDHC2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_ESDHC_C_SEL], MX51_MMC_SDHC3_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_ESDHC_D_SEL], MX51_MMC_SDHC4_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_IPG], MX51_ATA_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM1_BASE_ADDR, "per");
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clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM2_BASE_ADDR, "per");
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if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
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mx51_clocks_ipu_init(regs);
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return 0;
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}
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static int imx51_ccm_probe(struct device_d *dev)
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{
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void __iomem *regs;
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regs = dev_request_mem_region(dev, 0);
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mx51_clocks_init(regs, 32768, 24000000, 22579200, 0); /* FIXME */
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return 0;
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}
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static __maybe_unused struct of_device_id imx51_ccm_dt_ids[] = {
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{
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.compatible = "fsl,imx51-ccm",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d imx51_ccm_driver = {
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.probe = imx51_ccm_probe,
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.name = "imx51-ccm",
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.of_compatible = DRV_OF_COMPAT(imx51_ccm_dt_ids),
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};
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static void mx53_clocks_ipu_init(void __iomem *regs)
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{
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clks[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
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clks[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", regs + CCM_CSCMR2, 11, 1);
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clks[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_p("ldb_di1_sel", regs + CCM_CSCMR2, 9, 1,
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mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel));
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clks[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", regs + CCM_CDCDR, 16, 3);
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clks[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
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clks[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider("ldb_di0_div", "ldb_di0_div_3_5", regs + CCM_CSCMR2, 10, 1);
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clks[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_p("ldb_di0_sel", regs + CCM_CSCMR2, 8, 1,
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|
mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel));
|
|
clks[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_p("ipu_di0_sel", regs + CCM_CSCMR2, 26, 3,
|
|
mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
|
|
clks[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_p("ipu_di1_sel", regs + CCM_CSCMR2, 29, 3,
|
|
mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
|
|
clks[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_p("tve_ext_sel", regs + CCM_CSCMR1, 6, 1,
|
|
mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel));
|
|
clks[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", regs + CCM_CDCDR, 28, 3);
|
|
|
|
mx5_clocks_ipu_init(regs);
|
|
|
|
clkdev_add_physbase(clks[IMX5_CLK_IPU_SEL], MX53_IPU_BASE_ADDR, "bus");
|
|
clkdev_add_physbase(clks[IMX5_CLK_IPU_DI0_SEL], MX53_IPU_BASE_ADDR, "di0");
|
|
clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX53_IPU_BASE_ADDR, "di1");
|
|
}
|
|
|
|
int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
|
|
unsigned long rate_ckih1, unsigned long rate_ckih2)
|
|
{
|
|
clks[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX53_PLL1_BASE_ADDR);
|
|
clks[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX53_PLL2_BASE_ADDR);
|
|
clks[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX53_PLL3_BASE_ADDR);
|
|
clks[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", (void *)MX53_PLL4_BASE_ADDR);
|
|
|
|
mx5_clocks_common_init(regs, rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
|
|
|
|
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART1_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART2_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART3_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C1_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C2_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C3_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_GPT1_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_IPG], MX53_CSPI_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_ECSPI_PODF], MX53_ECSPI1_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_ECSPI_PODF], MX53_ECSPI2_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_IPG], MX53_FEC_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_A_PODF], MX53_ESDHC1_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_C_SEL], MX53_ESDHC2_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_B_PODF], MX53_ESDHC3_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_D_SEL], MX53_ESDHC4_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_AHB], MX53_SATA_BASE_ADDR, NULL);
|
|
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM1_BASE_ADDR, "per");
|
|
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM2_BASE_ADDR, "per");
|
|
|
|
if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
|
|
mx53_clocks_ipu_init(regs);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int imx53_ccm_probe(struct device_d *dev)
|
|
{
|
|
void __iomem *regs;
|
|
|
|
regs = dev_request_mem_region(dev, 0);
|
|
|
|
mx53_clocks_init(regs, 32768, 24000000, 22579200, 0); /* FIXME */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static __maybe_unused struct of_device_id imx53_ccm_dt_ids[] = {
|
|
{
|
|
.compatible = "fsl,imx53-ccm",
|
|
}, {
|
|
/* sentinel */
|
|
}
|
|
};
|
|
|
|
static struct driver_d imx53_ccm_driver = {
|
|
.probe = imx53_ccm_probe,
|
|
.name = "imx53-ccm",
|
|
.of_compatible = DRV_OF_COMPAT(imx53_ccm_dt_ids),
|
|
};
|
|
|
|
static int imx5_ccm_init(void)
|
|
{
|
|
if (IS_ENABLED(CONFIG_ARCH_IMX51))
|
|
platform_driver_register(&imx51_ccm_driver);
|
|
if (IS_ENABLED(CONFIG_ARCH_IMX53))
|
|
platform_driver_register(&imx53_ccm_driver);
|
|
|
|
return 0;
|
|
}
|
|
core_initcall(imx5_ccm_init);
|