59 lines
1.4 KiB
C
59 lines
1.4 KiB
C
#include <common.h>
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#include <io.h>
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#include <sizes.h>
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#include <mach/imx5.h>
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#include <mach/clock-imx51_53.h>
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void imx5_setup_pll(void __iomem *base, int freq, u32 op, u32 mfd, u32 mfn)
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{
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u32 r;
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/*
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* If freq < 300MHz, we need to set dpdck0_2_en to 0
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*/
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r = 0x00000232;
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if (freq >= 300)
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r |= 0x1000;
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writel(r, base + MX5_PLL_DP_CTL);
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writel(0x2, base + MX5_PLL_DP_CONFIG);
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writel(op, base + MX5_PLL_DP_OP);
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writel(op, base + MX5_PLL_DP_HFS_OP);
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writel(mfd, base + MX5_PLL_DP_MFD);
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writel(mfd, base + MX5_PLL_DP_HFS_MFD);
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writel(mfn, base + MX5_PLL_DP_MFN);
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writel(mfn, base + MX5_PLL_DP_HFS_MFN);
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writel(0x00001232, base + MX5_PLL_DP_CTL);
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while (!(readl(base + MX5_PLL_DP_CTL) & 1));
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}
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void imx5_init_lowlevel(void)
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{
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u32 r;
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/* ARM errata ID #468414 */
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__asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r));
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r |= (1 << 5); /* enable L1NEON bit */
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r &= ~(1 << 1); /* explicitly disable L2 cache */
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__asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r));
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/* reconfigure L2 cache aux control reg */
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r = 0xc0 | /* tag RAM */
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0x4 | /* data RAM */
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(1 << 24) | /* disable write allocate delay */
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(1 << 23) | /* disable write allocate combine */
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(1 << 22); /* disable write allocate */
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__asm__ __volatile__("mcr 15, 1, %0, c9, c0, 2" : : "r"(r));
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__asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r));
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r |= 1 << 1; /* enable L2 cache */
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__asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r));
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}
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