19 lines
651 B
C
19 lines
651 B
C
#ifndef __MACH_SOCFPGA_REGS_H
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#define __MACH_SOCFPGA_REGS_H
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#define CYCLONE5_SDMMC_ADDRESS 0xff704000
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#define CYCLONE5_GPIO0_BASE 0xff708000
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#define CYCLONE5_GPIO1_BASE 0xff709000
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#define CYCLONE5_GPIO2_BASE 0xff70A000
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#define CYCLONE5_L3REGS_ADDRESS 0xff800000
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#define CYCLONE5_UART0_ADDRESS 0xffc02000
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#define CYCLONE5_UART1_ADDRESS 0xffc03000
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#define CYCLONE5_SDR_ADDRESS 0xffc20000
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#define CYCLONE5_CLKMGR_ADDRESS 0xffd04000
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#define CYCLONE5_RSTMGR_ADDRESS 0xffd05000
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#define CYCLONE5_SYSMGR_ADDRESS 0xffd08000
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#define CYCLONE5_SCANMGR_ADDRESS 0xfff02000
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#define CYCLONE5_SMP_TWD_ADDRESS 0xfffec600
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#endif /* __MACH_SOCFPGA_REGS_H */
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