70 lines
1.9 KiB
C
70 lines
1.9 KiB
C
/**
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* @file
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* @brief Global defintions for the ARM S3C2440 based a9m2440 CPU card
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*/
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/* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/**
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* The external clock reference is a 16.9344 MHz crystal
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*/
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#define S3C24XX_CLOCK_REFERENCE 16934400
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/**
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* Define the main clock configuration to be used in register CLKDIVN
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*
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* We must limit the frequency of the connected SDRAMs with the clock ratio
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* setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 400Mhz:100MHz:50MHz
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*/
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#define BOARD_SPECIFIC_CLKDIVN 0x05
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/**
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* Define the MPLL configuration to be used in register MPLLCON
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*
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* We want the MPLL to run at 399.65 MHz
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*/
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#define BOARD_SPECIFIC_MPLL ((0x6e << 12) + (3 << 4) + 1)
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/**
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* Define the UPLL configuration to be used in register UPLLCON
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*
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* We want the UPLL to run at 47.98 MHz
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*/
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#define BOARD_SPECIFIC_UPLL ((0x3c << 12) + (4 << 4) + 2)
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/*
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* Flash access timings
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* Tacls = 0ns (but 20ns data setup time)
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* Twrph0 = 25ns (write) 35ns (read)
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* Twrph1 = 10ns (10ns data hold time)
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* Read cycle time = 50ns
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*
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* Assumed HCLK is 100MHz
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* Tacls = 1 (-> 20ns)
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* Twrph0 = 3 (-> 40ns)
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* Twrph1 = 1 (-> 20ns)
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* Cycle time = 80ns
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*/
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#define A9M2440_TACLS 1
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#define A9M2440_TWRPH0 3
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#define A9M2440_TWRPH1 1
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/* needed in the generic NAND boot code only */
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#ifdef CONFIG_S3C_NAND_BOOT
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# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1)
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#endif
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#endif /* __CONFIG_H */
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