166 lines
4.9 KiB
C
166 lines
4.9 KiB
C
/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <mach/imx-regs.h>
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#include <mach/imx-pll.h>
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#include <mach/esdctl.h>
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#include <io.h>
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#include <mach/imx-nand.h>
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#include <asm/barebox-arm.h>
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#include <asm-generic/sections.h>
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#include <asm-generic/memory_layout.h>
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#include <asm/system.h>
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#ifdef CONFIG_NAND_IMX_BOOT
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static void __bare_init __naked insdram(void)
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{
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uint32_t r;
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/* setup a stack to be able to call imx_nand_load_image() */
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r = STACK_BASE + STACK_SIZE - 12;
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__asm__ __volatile__("mov sp, %0" : : "r"(r));
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imx_nand_load_image(_text, barebox_image_size);
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board_init_lowlevel_return();
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}
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#endif
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void __bare_init __naked board_init_lowlevel(void)
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{
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uint32_t r;
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#ifdef CONFIG_NAND_IMX_BOOT
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unsigned int *trg, *src;
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int i;
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#endif
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register uint32_t loops = 0x20000;
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/* restart the MPLL and wait until it's stable */
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writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27),
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IMX_CCM_BASE + CCM_CCTL);
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while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {};
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/* Configure dividers and ARM clock source
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* ARM @ 400 MHz
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* AHB @ 133 MHz
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*/
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writel(0x20034000, IMX_CCM_BASE + CCM_CCTL);
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/* Enable UART1 / FEC / */
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/* writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0);
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writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1);
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writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2);*/
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/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, 0x43f00000);
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writel(0x77777777, 0x43f00004);
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writel(0x77777777, 0x53f00000);
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writel(0x77777777, 0x53f00004);
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/* MAX (Multi-Layer AHB Crossbar Switch) setup
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* MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
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*/
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writel(0x00002143, 0x43f04000);
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writel(0x00002143, 0x43f04100);
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writel(0x00002143, 0x43f04200);
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writel(0x00002143, 0x43f04300);
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writel(0x00002143, 0x43f04400);
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/* SGPCR - always park on last master */
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writel(0x10, 0x43f04010);
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writel(0x10, 0x43f04110);
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writel(0x10, 0x43f04210);
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writel(0x10, 0x43f04310);
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writel(0x10, 0x43f04410);
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/* MGPCR - restore default values */
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writel(0x0, 0x43f04800);
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writel(0x0, 0x43f04900);
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writel(0x0, 0x43f04a00);
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writel(0x0, 0x43f04b00);
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writel(0x0, 0x43f04c00);
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/* Configure M3IF registers
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* M3IF Control Register (M3IFCTL) for MX25
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* MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
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* MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
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* MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
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* MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
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* MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000
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* MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000
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* MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
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* ----------
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* 0x00000001
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*/
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writel(0x1, 0xb8003000);
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/* Speed up NAND controller by adjusting the NFC divider */
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r = readl(IMX_CCM_BASE + CCM_PCDR2);
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r &= ~0xf;
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r |= 0x1;
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writel(r, IMX_CCM_BASE + CCM_PCDR2);
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/* Skip SDRAM initialization if we run from RAM */
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r = get_pc();
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if (r > 0x80000000 && r < 0x90000000)
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board_init_lowlevel_return();
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/* Init Mobile DDR */
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writel(0x0000000E, ESDMISC);
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writel(0x00000004, ESDMISC);
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0" (loops));
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writel(0x0029572B, ESDCFG0);
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writel(0x92210000, ESDCTL0);
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writeb(0xda, IMX_SDRAM_CS0 + 0x400);
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writel(0xA2210000, ESDCTL0);
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writeb(0xda, IMX_SDRAM_CS0);
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writeb(0xda, IMX_SDRAM_CS0);
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writel(0xB2210000, ESDCTL0);
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writeb(0xda, IMX_SDRAM_CS0 + 0x33);
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writeb(0xda, IMX_SDRAM_CS0 + 0x1000000);
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writel(0x82216080, ESDCTL0);
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#ifdef CONFIG_NAND_IMX_BOOT
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/* skip NAND boot if not running from NFC space */
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r = get_pc();
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if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
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board_init_lowlevel_return();
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src = (unsigned int *)IMX_NFC_BASE;
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trg = (unsigned int *)_text;
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/* Move ourselves out of NFC SRAM */
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for (i = 0; i < 0x800 / sizeof(int); i++)
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*trg++ = *src++;
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/* Jump to SDRAM */
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r = (unsigned int)&insdram;
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__asm__ __volatile__("mov pc, %0" : : "r"(r));
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#else
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board_init_lowlevel_return();
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#endif
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}
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