151 lines
3.9 KiB
C
151 lines
3.9 KiB
C
/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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* (c) 2011 Eukrea Electromatique, Eric Bénard <eric@eukrea.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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#include <common.h>
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#include <net.h>
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#include <init.h>
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#include <environment.h>
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#include <mach/imx-regs.h>
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#include <fec.h>
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#include <mach/gpio.h>
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#include <asm/armlinux.h>
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#include <generated/mach-types.h>
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
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#include <nand.h>
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#include <spi/spi.h>
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#include <io.h>
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#include <asm/mmu.h>
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#include <mach/imx-nand.h>
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#include <mach/spi.h>
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#include <mach/generic.h>
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#include <mach/imx5.h>
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#include <mach/iomux-mx51.h>
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#include <mach/devices-imx51.h>
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static struct fec_platform_data fec_info = {
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.xcv_type = MII100,
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};
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struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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.flash_bbt = 1,
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};
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static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
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/* UART1 */
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MX51_PAD_UART1_RXD__UART1_RXD,
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MX51_PAD_UART1_TXD__UART1_TXD,
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MX51_PAD_UART1_RTS__UART1_RTS,
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MX51_PAD_UART1_CTS__UART1_CTS,
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/* FEC */
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MX51_PAD_DISP2_DAT1__FEC_RX_ER,
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MX51_PAD_DISP2_DAT15__FEC_TDATA0,
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MX51_PAD_DISP2_DAT6__FEC_TDATA1,
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MX51_PAD_DISP2_DAT7__FEC_TDATA2,
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MX51_PAD_DISP2_DAT8__FEC_TDATA3,
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MX51_PAD_DISP2_DAT9__FEC_TX_EN,
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MX51_PAD_DISP2_DAT10__FEC_COL,
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MX51_PAD_DISP2_DAT11__FEC_RX_CLK,
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MX51_PAD_DISP2_DAT12__FEC_RX_DV,
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MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
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MX51_PAD_DI2_PIN4__FEC_CRS,
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MX51_PAD_DI2_PIN2__FEC_MDC,
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MX51_PAD_DI2_PIN3__FEC_MDIO,
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MX51_PAD_DISP2_DAT14__FEC_RDATA0,
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MX51_PAD_DI2_DISP_CLK__FEC_RDATA1,
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MX51_PAD_DI_GP4__FEC_RDATA2,
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MX51_PAD_DISP2_DAT0__FEC_RDATA3,
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MX51_PAD_DI_GP3__FEC_TX_ER,
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MX51_PAD_EIM_DTACK__GPIO2_31, /* LAN8700 reset pin */
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/* NAND */
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MX51_PAD_NANDF_D7__NANDF_D7,
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MX51_PAD_NANDF_D6__NANDF_D6,
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MX51_PAD_NANDF_D5__NANDF_D5,
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MX51_PAD_NANDF_D4__NANDF_D4,
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MX51_PAD_NANDF_D3__NANDF_D3,
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MX51_PAD_NANDF_D2__NANDF_D2,
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MX51_PAD_NANDF_D1__NANDF_D1,
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MX51_PAD_NANDF_D0__NANDF_D0,
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MX51_PAD_NANDF_RB0__NANDF_RB0,
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MX51_PAD_NANDF_RB1__NANDF_RB1,
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MX51_PAD_NANDF_CS0__NANDF_CS0,
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MX51_PAD_NANDF_CS1__NANDF_CS1,
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/* LCD BL */
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MX51_PAD_DI1_D1_CS__GPIO3_4,
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#ifdef CONFIG_MCI_IMX_ESDHC
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/* SD 1 */
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MX51_PAD_SD1_CMD__SD1_CMD,
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MX51_PAD_SD1_CLK__SD1_CLK,
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MX51_PAD_SD1_DATA0__SD1_DATA0,
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MX51_PAD_SD1_DATA1__SD1_DATA1,
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MX51_PAD_SD1_DATA2__SD1_DATA2,
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MX51_PAD_SD1_DATA3__SD1_DATA3,
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#endif
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};
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#define GPIO_LAN8700_RESET (1 * 32 + 31)
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#define GPIO_LCD_BL (2 * 32 + 4)
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static int eukrea_cpuimx51_mem_init(void)
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{
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arm_add_mem_device("ram0", 0x90000000, 256 * 1024 * 1024);
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return 0;
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}
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mem_initcall(eukrea_cpuimx51_mem_init);
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static int eukrea_cpuimx51_devices_init(void)
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{
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imx51_add_fec(&fec_info);
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#ifdef CONFIG_MCI_IMX_ESDHC
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imx51_add_mmc0(NULL);
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#endif
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imx51_add_nand(&nand_info);
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devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
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dev_add_bb_dev("self_raw", "self0");
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devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
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dev_add_bb_dev("env_raw", "env0");
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gpio_direction_output(GPIO_LAN8700_RESET, 0);
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gpio_set_value(GPIO_LAN8700_RESET, 1);
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gpio_direction_output(GPIO_LCD_BL, 0);
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armlinux_set_bootparams((void *)0x90000100);
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armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX51SD);
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return 0;
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}
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device_initcall(eukrea_cpuimx51_devices_init);
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static int eukrea_cpuimx51_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, ARRAY_SIZE(eukrea_cpuimx51_pads));
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imx51_init_lowlevel(800);
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imx51_add_uart0();
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return 0;
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}
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console_initcall(eukrea_cpuimx51_console_init);
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