452 lines
11 KiB
C
452 lines
11 KiB
C
/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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* 2009 Marc Kleine-Budde, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* Derived from:
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*
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* * mx35_3stack.c - board file for uboot-v1
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
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*
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*/
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#include <common.h>
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#include <environment.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <fec.h>
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#include <fs.h>
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#include <init.h>
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#include <nand.h>
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#include <net.h>
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#include <partition.h>
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#include <asm/armlinux.h>
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#include <asm-generic/sections.h>
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#include <asm/barebox-arm.h>
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#include <io.h>
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#include <generated/mach-types.h>
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#include <mach/gpio.h>
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#include <mach/imx-nand.h>
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#include <mach/imx-regs.h>
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#include <mach/iomux-mx35.h>
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#include <mach/iomux-v3.h>
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#include <mach/imx-ipu-fb.h>
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#include <mach/generic.h>
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#include <mach/devices-imx35.h>
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#include <i2c/i2c.h>
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#include <mfd/mc13xxx.h>
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#include <mfd/mc9sdz60.h>
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/* Board rev for the PDK 3stack */
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#define MX35PDK_BOARD_REV_1 0
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#define MX35PDK_BOARD_REV_2 1
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static struct fec_platform_data fec_info = {
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.xcv_type = MII100,
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.phy_addr = 0x1F,
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};
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struct imx_nand_platform_data nand_info = {
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.hw_ecc = 1,
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.flash_bbt = 1,
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};
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static struct i2c_board_info i2c_devices[] = {
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{
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I2C_BOARD_INFO("mc13xxx-i2c", 0x08),
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}, {
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I2C_BOARD_INFO("mc9sdz60", 0x69),
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},
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};
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/*
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* Generic display, shipped with the PDK
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*/
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static struct fb_videomode CTP_CLAA070LC0ACW = {
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/* 800x480 @ 60 Hz */
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.name = "CTP-CLAA070LC0ACW",
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.refresh = 60,
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.xres = 800,
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.yres = 480,
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.pixclock = KHZ2PICOS(27000),
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.left_margin = 50,
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.right_margin = 50, /* whole line should have 900 clocks */
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.upper_margin = 10,
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.lower_margin = 10, /* whole frame should have 500 lines */
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.hsync_len = 1, /* note: DE only display */
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.vsync_len = 1, /* note: DE only display */
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.sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
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.vmode = FB_VMODE_NONINTERLACED,
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.flag = 0,
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};
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static struct imx_ipu_fb_platform_data ipu_fb_data = {
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.mode = &CTP_CLAA070LC0ACW,
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.num_modes = 1,
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.bpp = 16,
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};
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/*
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* Revision to be passed to kernel. The kernel provided
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* by freescale relies on this.
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*
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* C --> CPU type
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* S --> Silicon revision
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* B --> Board rev
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*
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* 31 20 16 12 8 4 0
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* | Cmaj | Cmin | B | Smaj | Smin|
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*
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* e.g 0x00035120 --> i.MX35, Cpu silicon rev 2.0, Board rev 2
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*/
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static unsigned int imx35_3ds_system_rev = 0x00035000;
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static void set_silicon_rev( int rev)
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{
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imx35_3ds_system_rev = imx35_3ds_system_rev | (rev & 0xFF);
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}
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static void set_board_rev(int rev)
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{
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imx35_3ds_system_rev = (imx35_3ds_system_rev & ~(0xF << 8)) | (rev & 0xF) << 8;
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}
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static int f3s_mem_init(void)
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{
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arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
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arm_add_mem_device("ram1", IMX_SDRAM_CS1, 128 * 1024 * 1024);
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return 0;
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}
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mem_initcall(f3s_mem_init);
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static int f3s_devices_init(void)
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{
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uint32_t reg;
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/* CS0: Nor Flash */
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writel(0x0000cf03, CSCR_U(0));
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writel(0x10000d03, CSCR_L(0));
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writel(0x00720900, CSCR_A(0));
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reg = readl(IMX_CCM_BASE + CCM_RCSR);
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/* some fuses provide us vital information about connected hardware */
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if (reg & 0x20000000)
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nand_info.width = 2; /* 16 bit */
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else
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nand_info.width = 1; /* 8 bit */
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/*
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* This platform supports NOR and NAND
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*/
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imx35_add_nand(&nand_info);
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add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, 64 * 1024 * 1024, 0);
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switch ((reg >> 25) & 0x3) {
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case 0x01: /* NAND is the source */
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devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
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dev_add_bb_dev("self_raw", "self0");
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devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
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dev_add_bb_dev("env_raw", "env0");
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break;
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case 0x00: /* NOR is the source */
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devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
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devfs_add_partition("nor0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env0");
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protect_file("/dev/env0", 1);
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break;
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}
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set_silicon_rev(imx_silicon_revision());
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i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
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imx35_add_i2c0(NULL);
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imx35_add_fec(&fec_info);
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add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, IMX_CS5_BASE, IMX_CS5_RANGE,
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IORESOURCE_MEM, NULL);
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imx35_add_mmc0(NULL);
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imx35_add_fb(&ipu_fb_data);
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armlinux_set_bootparams((void *)0x80000100);
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armlinux_set_architecture(MACH_TYPE_MX35_3DS);
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return 0;
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}
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device_initcall(f3s_devices_init);
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static int f3s_enable_display(void)
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{
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/* Enable power to the LCD. (bit 6 hi.) */
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mc9sdz60_set_bits(mc9sdz60_get(), MC9SDZ60_REG_GPIO_1, 0x40, 0x40);
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return 0;
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}
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late_initcall(f3s_enable_display);
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static iomux_v3_cfg_t f3s_pads[] = {
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MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
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MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
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MX35_PAD_FEC_RX_DV__FEC_RX_DV,
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MX35_PAD_FEC_COL__FEC_COL,
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MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
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MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
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MX35_PAD_FEC_TX_EN__FEC_TX_EN,
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MX35_PAD_FEC_MDC__FEC_MDC,
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MX35_PAD_FEC_MDIO__FEC_MDIO,
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MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
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MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
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MX35_PAD_FEC_CRS__FEC_CRS,
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MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
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MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
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MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
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MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
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MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
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MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
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MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
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MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
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MX35_PAD_RXD1__UART1_RXD_MUX,
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MX35_PAD_TXD1__UART1_TXD_MUX,
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MX35_PAD_RTS1__UART1_RTS,
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MX35_PAD_CTS1__UART1_CTS,
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MX35_PAD_I2C1_CLK__I2C1_SCL,
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MX35_PAD_I2C1_DAT__I2C1_SDA,
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MX35_PAD_WDOG_RST__GPIO1_6,
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MX35_PAD_COMPARE__GPIO1_5,
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/* Display */
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MX35_PAD_LD0__IPU_DISPB_DAT_0,
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MX35_PAD_LD1__IPU_DISPB_DAT_1,
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MX35_PAD_LD2__IPU_DISPB_DAT_2,
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MX35_PAD_LD3__IPU_DISPB_DAT_3,
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MX35_PAD_LD4__IPU_DISPB_DAT_4,
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MX35_PAD_LD5__IPU_DISPB_DAT_5,
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MX35_PAD_LD6__IPU_DISPB_DAT_6,
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MX35_PAD_LD7__IPU_DISPB_DAT_7,
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MX35_PAD_LD8__IPU_DISPB_DAT_8,
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MX35_PAD_LD9__IPU_DISPB_DAT_9,
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MX35_PAD_LD10__IPU_DISPB_DAT_10,
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MX35_PAD_LD11__IPU_DISPB_DAT_11,
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MX35_PAD_LD12__IPU_DISPB_DAT_12,
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MX35_PAD_LD13__IPU_DISPB_DAT_13,
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MX35_PAD_LD14__IPU_DISPB_DAT_14,
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MX35_PAD_LD15__IPU_DISPB_DAT_15,
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MX35_PAD_LD16__IPU_DISPB_DAT_16,
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MX35_PAD_LD17__IPU_DISPB_DAT_17,
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MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
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MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
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MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
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MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
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MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
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MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
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MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
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};
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static int f3s_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads));
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imx35_add_uart0();
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return 0;
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}
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console_initcall(f3s_console_init);
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static int f3s_core_init(void)
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{
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u32 reg;
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writel(0x0000D843, CSCR_U(5)); /* CS5: smc9117 */
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writel(0x22252521, CSCR_L(5));
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writel(0x22220A00, CSCR_A(5));
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/* enable clock for I2C1 and FEC */
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reg = readl(IMX_CCM_BASE + CCM_CGR1);
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reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
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reg |= 0x3 << CCM_CGR1_I2C1_SHIFT;
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reg = writel(reg, IMX_CCM_BASE + CCM_CGR1);
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/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, IMX_AIPS1_BASE);
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writel(0x77777777, IMX_AIPS1_BASE + 0x4);
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writel(0x77777777, IMX_AIPS2_BASE);
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writel(0x77777777, IMX_AIPS2_BASE + 0x4);
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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writel(0x0, IMX_AIPS1_BASE + 0x40);
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writel(0x0, IMX_AIPS1_BASE + 0x44);
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writel(0x0, IMX_AIPS1_BASE + 0x48);
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writel(0x0, IMX_AIPS1_BASE + 0x4C);
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reg = readl(IMX_AIPS1_BASE + 0x50);
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reg &= 0x00FFFFFF;
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writel(reg, IMX_AIPS1_BASE + 0x50);
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writel(0x0, IMX_AIPS2_BASE + 0x40);
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writel(0x0, IMX_AIPS2_BASE + 0x44);
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writel(0x0, IMX_AIPS2_BASE + 0x48);
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writel(0x0, IMX_AIPS2_BASE + 0x4C);
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reg = readl(IMX_AIPS2_BASE + 0x50);
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reg &= 0x00FFFFFF;
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writel(reg, IMX_AIPS2_BASE + 0x50);
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/* MAX (Multi-Layer AHB Crossbar Switch) setup */
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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#define MAX_PARAM1 0x00302154
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
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/* SGPCR - always park on last master */
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writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */
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writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */
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writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */
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writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */
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writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */
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/* MGPCR - restore default values */
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writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */
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writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */
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writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */
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writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */
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writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */
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writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */
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return 0;
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}
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core_initcall(f3s_core_init);
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static int f3s_get_rev(struct mc13xxx *mc13xxx)
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{
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u32 rev;
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int err;
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err = mc13xxx_reg_read(mc13xxx, MC13XXX_REG_IDENTIFICATION, &rev);
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if (err)
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return err;
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if (rev == 0x00ffffff)
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return -ENODEV;
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return ((rev >> 6) & 0x7) ? MX35PDK_BOARD_REV_2 : MX35PDK_BOARD_REV_1;
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}
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static int f3s_pmic_init_v2(struct mc13xxx *mc13xxx)
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{
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int err = 0;
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/* COMPARE pin (GPIO1_5) as output and set high */
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gpio_direction_output( 32*0 + 5 , 1);
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err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_SETTING_0, 0x03, 0x03);
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err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_MODE_0, 0x01, 0x01);
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if (err)
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printf("mc13892 Init sequence failed, the system might not be working!\n");
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return err;
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}
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static int f3s_pmic_init_all(struct mc9sdz60 *mc9sdz60)
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{
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int err = 0;
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err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_GPIO_1, 0x04, 0x04);
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err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x00);
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mdelay(200);
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err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x80);
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if (err)
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dev_err(&mc9sdz60->client->dev,
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"Init sequence failed, the system might not be working!\n");
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return err;
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}
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static int f3s_pmic_init(void)
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{
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struct mc13xxx *mc13xxx;
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struct mc9sdz60 *mc9sdz60;
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int rev;
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mc13xxx = mc13xxx_get();
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if (!mc13xxx) {
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printf("FAILED to get PMIC handle!\n");
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return 0;
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}
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rev = f3s_get_rev(mc13xxx);
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switch (rev) {
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case MX35PDK_BOARD_REV_1:
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break;
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case MX35PDK_BOARD_REV_2:
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f3s_pmic_init_v2(mc13xxx);
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break;
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default:
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printf("FAILED to identify board revision!\n");
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return 0;
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}
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set_board_rev(rev);
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printf("i.MX35 PDK CPU board version %d.\n", rev );
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mc9sdz60 = mc9sdz60_get();
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if (!mc9sdz60) {
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printf("FAILED to get mc9sdz60 handle!\n");
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return 0;
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}
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f3s_pmic_init_all(mc9sdz60);
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armlinux_set_revision(imx35_3ds_system_rev);
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return 0;
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}
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late_initcall(f3s_pmic_init);
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#ifdef CONFIG_NAND_IMX_BOOT
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void __bare_init nand_boot(void)
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{
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/*
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* The driver is able to detect NAND's pagesize by CPU internal
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* fuses or external pull ups. But not the blocksize...
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|
*/
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imx_nand_load_image(_text, barebox_image_size);
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board_init_lowlevel_return();
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}
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#endif
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