268 lines
7.0 KiB
C
268 lines
7.0 KiB
C
/**
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* @file
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* @brief Board Initialization routines for OMAP3EVM.
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*
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* FileName: arch/arm/boards/omap/board-omap3evm.c
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*
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* This board is based on OMAP3530.
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* More on OMAP3530 (including documentation can be found here):
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* http://focus.ti.com/docs/prod/folders/print/omap3530.html
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*
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* This file provides initialization in two stages:
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* @li Boot time initialization - just get SDRAM working.
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* This is run from SRAM - so no case constructs and global vars can be used.
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* @li Run time initialization - this is for the rest of the initializations
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* such as flash, uart etc.
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*
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* Boot time initialization includes:
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* @li SDRAM initialization.
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* @li Pin Muxing relevant for the EVM.
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*
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* Run time initialization includes
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* @li serial @ref serial_ns16550.c driver device definition
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*
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* Originally from arch/arm/boards/omap/board-beagle.c
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*/
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/*
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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* Sanjeev Premi <premi@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <console.h>
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#include <init.h>
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#include <driver.h>
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#include <io.h>
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#include <sizes.h>
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#include <ns16550.h>
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#include <asm/armlinux.h>
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#include <mach/silicon.h>
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#include <mach/sdrc.h>
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#include <mach/sys_info.h>
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#include <mach/syslib.h>
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#include <mach/control.h>
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#include <mach/omap3-mux.h>
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#include <mach/gpmc.h>
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#include <errno.h>
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#include <generated/mach-types.h>
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/*
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* Boot-time initialization(s)
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*/
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/**
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* @brief Initialize the SDRC module
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*
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* @return void
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*/
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static void sdrc_init(void)
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{
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/* SDRAM software reset */
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/* No idle ack and RESET enable */
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writel(0x1A, SDRC_REG(SYSCONFIG));
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sdelay(100);
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/* No idle ack and RESET disable */
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writel(0x18, SDRC_REG(SYSCONFIG));
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/* SDRC Sharing register */
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/* 32-bit SDRAM on data lane [31:0] - CS0 */
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/* pin tri-stated = 1 */
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writel(0x00000100, SDRC_REG(SHARING));
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/* ----- SDRC Registers Configuration --------- */
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/* SDRC_MCFG0 register */
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writel(0x02584099, SDRC_REG(MCFG_0));
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/* SDRC_RFR_CTRL0 register */
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writel(0x54601, SDRC_REG(RFR_CTRL_0));
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/* SDRC_ACTIM_CTRLA0 register */
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writel(0xA29DB4C6, SDRC_REG(ACTIM_CTRLA_0));
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/* SDRC_ACTIM_CTRLB0 register */
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writel(0x12214, SDRC_REG(ACTIM_CTRLB_0));
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/* Disble Power Down of CKE due to 1 CKE on combo part */
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writel(0x00000081, SDRC_REG(POWER));
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/* SDRC_MANUAL command register */
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/* NOP command */
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writel(0x00000000, SDRC_REG(MANUAL_0));
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/* Precharge command */
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writel(0x00000001, SDRC_REG(MANUAL_0));
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/* Auto-refresh command */
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writel(0x00000002, SDRC_REG(MANUAL_0));
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/* Auto-refresh command */
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writel(0x00000002, SDRC_REG(MANUAL_0));
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/* SDRC MR0 register Burst length=4 */
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writel(0x00000032, SDRC_REG(MR_0));
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/* SDRC DLLA control register */
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writel(0x0000000A, SDRC_REG(DLLA_CTRL));
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return;
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}
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/**
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* @brief Do the necessary pin muxing required for OMAP3EVM. Some pins in OMAP3
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* do not have alternate modes. We don't program these pins.
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*
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* See @ref MUX_VAL for description of the muxing mode.
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*
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* @return void
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*/
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static void mux_config(void)
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{
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/*
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* SDRC
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* - SDRC_D0-SDRC_D31: Default MUX mode is mode0.
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*/
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/*
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* GPMC
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* - GPMC_D0-GPMC_D7: Default MUX mode is mode0.
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* - GPMC_NADV_ALE: Default MUX mode is mode0.
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* - GPMC_NOE: Default MUX mode is mode0.
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* - GPMC_NWE: Default MUX mode is mode0.
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* - GPMC_WAIT0: Default MUX mode is mode0.
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*/
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MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
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/*
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* Serial Interface
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*/
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#if defined(CONFIG_OMAP3EVM_UART1)
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MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
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MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
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#elif defined(CONFIG_OMAP3EVM_UART3)
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MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
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MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
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#endif
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}
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/**
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* @brief The basic entry point for board initialization.
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*
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* This is called as part of machine init (after arch init).
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* This is again called with stack in SRAM, so not too many
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* constructs possible here.
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*
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* @return void
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*/
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static int omap3_evm_board_init(void)
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{
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int in_sdram = running_in_sdram();
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omap3_core_init();
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mux_config();
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/* Dont reconfigure SDRAM while running in SDRAM! */
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if (!in_sdram)
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sdrc_init();
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return 0;
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}
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pure_initcall(omap3_evm_board_init);
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/*
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* Run-time initialization(s)
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*/
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#ifdef CONFIG_DRIVER_SERIAL_NS16550
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static struct NS16550_plat serial_plat = {
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.clock = 48000000, /* 48MHz (APLL96/2) */
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.shift = 2,
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};
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/**
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* @brief Initialize the serial port to be used as console.
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*
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* @return result of device registration
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*/
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static int omap3evm_init_console(void)
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{
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add_ns16550_device(DEVICE_ID_DYNAMIC,
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#if defined(CONFIG_OMAP3EVM_UART1)
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OMAP_UART1_BASE,
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#elif defined(CONFIG_OMAP3EVM_UART3)
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OMAP_UART3_BASE,
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#endif
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1024, IORESOURCE_MEM_8BIT, &serial_plat);
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return 0;
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}
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console_initcall(omap3evm_init_console);
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#endif /* CONFIG_DRIVER_SERIAL_NS16550 */
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static int omap3evm_mem_init(void)
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{
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arm_add_mem_device("ram0", 0x80000000, 128 * 1024 * 1024);
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return 0;
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}
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mem_initcall(omap3evm_mem_init);
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static int omap3evm_init_devices(void)
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{
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#ifdef CONFIG_OMAP_GPMC
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/*
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* WP is made high and WAIT1 active Low
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*/
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gpmc_generic_init(0x10);
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#endif
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#ifdef CONFIG_MCI_OMAP_HSMMC
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add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, OMAP_MMC1_BASE, SZ_4K,
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IORESOURCE_MEM, NULL);
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#endif
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armlinux_set_bootparams((void *)0x80000100);
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armlinux_set_architecture(MACH_TYPE_OMAP3EVM);
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return 0;
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}
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device_initcall(omap3evm_init_devices);
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