325 lines
11 KiB
C
325 lines
11 KiB
C
/*
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* Copyright (C) 2005 Phytec Messtechnik GmbH
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* Juergen Kilb, H. Klaholz <armlinux@phytec.de>
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*
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* Copyright (C) 2006 Pengutronix
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* Sascha Hauer <s.hauer@pengutronix.de>
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* Robert Schwebel <r.schwebel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* phyCORE-PXA270 configuration settings
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* Set these to 0/1 to enable or disable the features.
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*/
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#define PHYCORE_PXA270_USE_K3FLASH 0
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/* 260 MHz or 520 MHZ */
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#define PHYCORE_PXA270_SPEED 520
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/*********************************************************************
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* CONFIG PXA270 GPIO settings *
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*********************************************************************/
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/*
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* GPIO set "1"
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*
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*** REG GPSR0
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* GP15 == nCS1 is 1
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* GP20 == nSDCS2 is 1
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* GP21 == nSDCS3 is 1
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*** REG GPSR1
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* GP33 == nCS5 is 1
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*** REG GPSR2
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* GP78 == nCS2 is 1
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* GP80 == nCS4 is 1
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*/
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#define GPSR0_DFT 0x00308000
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#define GPSR1_DFT 0x00000002
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#define GPSR2_DFT 0x00014000
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#define CONFIG_GPSR0_VAL GPSR0_DFT
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#define CONFIG_GPSR1_VAL GPSR1_DFT
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#define CONFIG_GPSR2_VAL GPSR2_DFT
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#define CONFIG_GPSR3_VAL GPSR3_DFT
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/*
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* set Direction "1" GPIO == output else input
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*
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** REG GPDR0
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* GP03 == PWR_SDA is output
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* GP04 == PWR_SCL is output
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* GP15 == nCS1 is output
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* GP20 == nSDCS2 is output
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* GP21 == nSDCS3 is output
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** REG GPDR1
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* GP33 == nCS5 is output
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** REG GPDR2
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* GP78 == nCS2 is output
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* GP80 == nCS4 is output
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* GP90 == LED0 is output
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* GP91 == LED1 is output
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*/
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#define GPDR0_DFT 0x00308018
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#define GPDR1_DFT 0x00000002
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#define GPDR2_DFT 0x00014000
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#define CONFIG_GPDR0_VAL GPDR0_DFT
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#define CONFIG_GPDR1_VAL GPDR1_DFT
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#define CONFIG_GPDR2_VAL GPDR2_DFT
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/*
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* set Alternate Funktions
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*
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** REG GAFR0_L
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* GP15 == nCS1 is AF10
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** REG GAFR0_U
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* GP18 == RDY is AF01
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* GP20 == nSDCS2 is AF01
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* GP21 == nSDCS3 is AF01
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** REG GAFR1_L
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* GP33 == nCS5 is AF10
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** REG GAFR2_L
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* GP78 == nCS2 is AF10
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** REG GAFR2_U
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* GP80 == nCS4 is AF10
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*/
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#define GAFR0_L_DFT 0x80000000
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#define GAFR0_U_DFT 0x00000510
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#define GAFR1_L_DFT 0x00000008
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#define GAFR1_U_DFT 0x00000000
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#define GAFR2_L_DFT 0x20000000
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#define GAFR2_U_DFT 0x00000002
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#define CONFIG_GAFR0_L_VAL GAFR0_L_DFT
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#define CONFIG_GAFR0_U_VAL GAFR0_U_DFT
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#define CONFIG_GAFR1_L_VAL GAFR1_L_DFT
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#define CONFIG_GAFR1_U_VAL GAFR1_U_DFT
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#define CONFIG_GAFR2_L_VAL GAFR2_L_DFT
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#define CONFIG_GAFR2_U_VAL GAFR2_U_DFT
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/*
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* Power Manager Sleep Status Register (PSSR)
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*
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* [6] = 0 OTG pad is not holding it's state
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* [5] = 1 Read Disable Hold: receivers of all gpio pins are disabled
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* [4] = 1 gpio pins are held in their sleep mode state
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* [3] = 0 The processor has not been placed in standby mode by
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* configuring the PWRMODE register since STS was cleared
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* by a reset or by software.
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* [2] = 1 nVDD_FAULT has been asserted and caused the processor to
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* enter deep-sleep mode.
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* [1] = 1 nBATT_FAULT has been asserted and caused the processor to
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* enter deep-sleep mode.
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* [0] = 1 The processor was placed in sleep mode by configuring the
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* PWRMODE register.
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*/
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#define CONFIG_PSSR_VAL 0x37
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/*********************************************************************
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* CONFIG PXA270 Chipselect settings *
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*********************************************************************/
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/*
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* Memory settings
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*
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* This is the configuration for nCS1/0 -> PLD / flash
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* configuration for nCS1:
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* [31] 0 - Slower Device
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* [30:28] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns
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* [27:24] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns
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* [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
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* [19] 1 - 16 Bit bus width
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* [18:16] 011 - burst RAM or FLASH
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* configuration for nCS0 (J3 Flash):
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* [15] 0 - Slower Device
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* [14:12] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns
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* [11:08] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns
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* [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
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* [03] 0 - 32 Bit bus width
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* [02:00] 011 - burst RAM or FLASH
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*/
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#if PHYCORE_PXA270_USE_K3FLASH == 0
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#define CONFIG_MSC0_VAL 0x128C1262
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#else
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/* configuration for nCS0 (K3 Flash):
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* [15] 0 - Slower Device
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* [14:12] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns
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* [11:08] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns
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* [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
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* [03] 0 - 32 Bit bus width
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* [02:00] 011 - burst RAM or FLASH
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*/
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#define CONFIG_MSC0_VAL 0x128C12B3
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#endif
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/*
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* This is the configuration for nCS3/2
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* configuration for nCS3: POWER
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*
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* [31] 0 - Slower Device
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* [30:28] 111 - RRR3: CS deselect to CS time: 7*(2*MemClk) = 140 ns
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* [27:24] 1111 - RDN3: Address to data valid in bursts: (15+1)*MemClk = 160 ns
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* [23:20] 1111 - RDF3: Address for first access: (23+1)*MemClk = 240 ns
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* [19] 0 - 32 Bit bus width
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* [18:16] 100 - variable latency I/O
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* configuration for nCS2: PLD
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* [15] 0 - Slower Device
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* [14:12] 111 - RRR2: CS deselect to CS time: 7*(2*MemClk) = 140 ns
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* [11:08] 1111 - RDN2: Address to data valid in bursts: (15+1)*MemClk = 160 ns
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* [07:04] 1111 - RDF2: Address for first access: (23+1)*MemClk = 240 ns
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* [03] 1 - 16 Bit bus width
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* [02:00] 100 - variable latency I/O
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*/
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#define CONFIG_MSC1_VAL 0x128c128c
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/*
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* This is the configuration for nCS5/4
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*
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* configuration for nCS5: LAN Controller
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* [31] 0 - Slower Device
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* [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
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* [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
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* [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
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* [19] 0 - 32 Bit bus width
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* [18:16] 100 - variable latency I/O
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* configuration for nCS4: USB
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* [15] 0 - Slower Device
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* [14:12] 111 - RRR4: CS deselect to CS time: 7*(2*MemClk) = 140 ns
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* [11:08] 1111 - RDN4: Address to data valid in bursts: (15+1)*MemClk = 160 ns
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* [07:04] 1111 - RDF4: Address for first access: (23+1)*MemClk = 240 ns
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* [03] 1 - 16 Bit bus width
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* [02:00] 100 - variable latency I/O
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*/
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#define CONFIG_MSC2_VAL 0x1234128C
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/*********************************************************************
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* CONFIG PXA270 SDRAM settings *
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*********************************************************************/
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#define CONFIG_DRAM_BASE 0xa0000000
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/* MDCNFG: SDRAM Configuration Register
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*
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* [31] 0 - Stack1
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* [30] 0 - dcacx2
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* [20] 0 - reserved
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* [31:29] 000 - reserved
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* [28] 1 - SA1111 compatiblity mode
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* [27] 1 - latch return data with return clock
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* [26] 0 - alternate addressing for pair 2/3
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* [25:24] 10 - timings
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* [23] 1 - internal banks in lower partition 2/3 (not used)
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* [22:21] 10 - row address bits for partition 2/3 (not used)
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* [20:19] 01 - column address bits for partition 2/3 (not used)
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* [18] 0 - SDRAM partition 2/3 width is 32 bit
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* [17] 0 - SDRAM partition 3 disabled
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* [16] 0 - SDRAM partition 2 disabled
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* [15] 0 - Stack1
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* [14] 0 - dcacx0
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* [13] 0 - Stack0
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* [12] 0 - SA1110 compatiblity mode
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* [11] 1 - always 1
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* [10] 0 - no alternate addressing for pair 0/1
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* [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
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* [7] 1 - 4 internal banks in lower partition pair
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* [06:05] 10 - 13 row address bits for partition 0/1
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* [04:03] 01 - 9 column address bits for partition 0/1
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* [02] 0 - SDRAM partition 0/1 width is 32 bit
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* [01] 0 - disable SDRAM partition 1
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* [00] 1 - enable SDRAM partition 0
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*/
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/* K4S561633*/
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#define CONFIG_MDCNFG_VAL 0x0AC90AC9
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/* MDREFR: SDRAM Refresh Control Register
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*
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* [31] 0 - ALTREFA
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* [30] 0 - ALTREFB
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* [29] 1 - K0DB4
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* [28] 0 - reserved
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* [27] 0 - reserved
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* [26] 0 - reserved
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* [25] 1 - K2FREE: not free running
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* [24] 0 - K1FREE: not free running
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* [23] 1 - K0FREE: not free running
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* [22] 0 - SLFRSH: self refresh disabled
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* [21] 0 - reserved
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* [20] 0 - APD: no auto power down
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* [19] 0 - K2DB2: SDCLK2 is MemClk
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* [18] 0 - K2RUN: disable SDCLK2
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* [17] 0 - K1DB2: SDCLK1 is MemClk
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* [16] 1 - K1RUN: enable SDCLK1
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* [15] 1 - E1PIN: SDRAM clock enable
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* [14] 1 - K0DB2: SDCLK0 is MemClk
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* [13] 0 - K0RUN: disable SDCLK0
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* [12] 0 - RESERVED
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* [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
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*/
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#define CONFIG_MDREFR_VAL 0x2281C018
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/* MDMRS: Mode Register Set Configuration Register
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*
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* [31] 0 - reserved
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* [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
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* [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
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* [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
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* [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
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* [15] 0 - reserved
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* [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
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* [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
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* [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
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* [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
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*/
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#define CONFIG_MDMRS_VAL 0x00020022
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/*********************************************************************
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* CONFIG PXA270 Clock generation *
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*********************************************************************/
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#define CONFIG_FLYCNFG_VAL 0x00010001
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#define CONFIG_SXCNFG_VAL 0x40044004
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#define CONFIG_CKEN (CKEN_MEMC | CKEN_OSTIMER)
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#if PHYCORE_PXA270_SPEED == 520
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#define CONFIG_CCCR 0x00000290 /* Memory Clock is f. Table; N=2.5, L=16 => 16x13=208, 208x2,5=520 MHz */
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#elif PHYCORE_PXA270_SPEED == 260
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#define CONFIG_CCCR 0x02000288 /* Memory Clock is System-Bus Freq., N=2.5, L=8 => 8x13=104, 104x2,5=260 MHz */
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#else
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#error You have specified an illegal speed.
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#endif
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/*********************************************************************
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* CONFIG PXA270 CF interface *
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*********************************************************************/
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#define CONFIG_MECR_VAL 0x00000003
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#define CONFIG_MCMEM0_VAL 0x00010504
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#define CONFIG_MCMEM1_VAL 0x00010504
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#define CONFIG_MCATT0_VAL 0x00010504
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#define CONFIG_MCATT1_VAL 0x00010504
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#define CONFIG_MCIO0_VAL 0x00004715
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#define CONFIG_MCIO1_VAL 0x00004715
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#endif /* __CONFIG_H */
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