453 lines
12 KiB
ArmAsm
453 lines
12 KiB
ArmAsm
/*
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* This was originally from the Lubbock u-boot port.
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*
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* Most of this taken from Redboot hal_platform_setup.h with cleanup
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*
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* NOTE: I haven't clean this up considerably, just enough to get it
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* running. See hal_platform_setup.h for the source. See
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* board/cradle/lowlevel_init.S for another PXA250 setup that is
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* much cleaner.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <config.h>
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#include <mach/pxa-regs.h>
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#include <mach/regs-ost.h>
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#include <mach/regs-intc.h>
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#define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO <31:00> */
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#define GPSR1 0x40E0001C /* GPIO Pin Output Set Register GPIO <63:32> */
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#define GPSR2 0x40E00020 /* GPIO Pin Output Set Register GPIO <80:64> */
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#define GPCR0 0x40E00024 /* GPIO Pin Output Clear Register GPIO <31:00> */
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#define GPCR1 0x40E00028 /* GPIO Pin Output Clear Register GPIO <63:32> */
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#define GPCR2 0x40E0002C /* GPIO Pin Output Clear Register GPIO <80:64> */
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#define GPDR0 0x40E0000C /* GPIO Pin Direction Register GPIO <31:0o> */
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#define GPDR1 0x40E00010 /* GPIO Pin Direction Register GPIO <63:32> */
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#define GPDR2 0x40E00014 /* GPIO Pin Direction Register GPIO <80:64> */
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#define GAFR0_L 0x40E00054 /* GPIO Alternate Function Select Register GPIO <15:00> */
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#define GAFR0_U 0x40E00058 /* GPIO Alternate Function Select Register GPIO <31:16> */
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#define GAFR1_L 0x40E0005C /* GPIO Alternate Function Select Register GPIO <47:32> */
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#define GAFR1_U 0x40E00060 /* GPIO Alternate Function Select Register GPIO <63:48> */
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#define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO <79:64> */
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#define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO <95:80> */
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/*
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* Memory setup
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*/
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.globl board_init_lowlevel
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board_init_lowlevel:
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@ Preserve r8/r7 i.e. kernel entry values
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@ Data cache might be active.
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@ Be sure to flush kernel binary out of the cache,
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@ whatever state it is, before it is turned off.
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@ This is done by fetching through currently executed
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@ memory to be sure we hit the same cache.
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bic r2, pc, #0x1f
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add r3, r2, #0x10000 @ 64 kb is quite enough...
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1: ldr r0, [r2], #32
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teq r2, r3
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bne 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
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@ disabling MMU and caches
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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bic r0, r0, #0x05 @ clear DC, MMU
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bic r0, r0, #0x1000 @ clear Icache
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mcr p15, 0, r0, c1, c0, 0
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/* set output */
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ldr r0, =GPSR0
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ldr r1, =CONFIG_GPSR0_VAL
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str r1, [r0]
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ldr r0, =GPSR1
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ldr r1, =CONFIG_GPSR1_VAL
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str r1, [r0]
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ldr r0, =GPSR2
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ldr r1, =CONFIG_GPSR2_VAL
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str r1, [r0]
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/* set direction */
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ldr r0, =GPDR0
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ldr r1, =CONFIG_GPDR0_VAL
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str r1, [r0]
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ldr r0, =GPDR1
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ldr r1, =CONFIG_GPDR1_VAL
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str r1, [r0]
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ldr r0, =GPDR2
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ldr r1, =CONFIG_GPDR2_VAL
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str r1, [r0]
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/* alternate function */
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ldr r0, =GAFR0_L
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ldr r1, =CONFIG_GAFR0_L_VAL
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str r1, [r0]
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ldr r0, =GAFR0_U
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ldr r1, =CONFIG_GAFR0_U_VAL
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str r1, [r0]
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ldr r0, =GAFR1_L
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ldr r1, =CONFIG_GAFR1_L_VAL
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str r1, [r0]
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ldr r0, =GAFR1_U
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ldr r1, =CONFIG_GAFR1_U_VAL
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str r1, [r0]
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ldr r0, =GAFR2_L
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ldr r1, =CONFIG_GAFR2_L_VAL
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str r1, [r0]
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ldr r0, =GAFR2_U
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ldr r1, =CONFIG_GAFR2_U_VAL
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str r1, [r0]
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/* enable GPIO pins */
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ldr r0, =PSSR
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ldr r1, =CONFIG_PSSR_VAL
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str r1, [r0]
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/* -------------------------------------------------------------------- */
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/* Enable memory interface */
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/* */
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/* The sequence below is based on the recommended init steps */
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/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
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/* Chapter 10. */
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/* -------------------------------------------------------------------- */
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/* -------------------------------------------------------------------- */
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/* Step 1: Wait for at least 200 microsedonds to allow internal */
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/* clocks to settle. Only necessary after hard reset... */
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/* FIXME: can be optimized later */
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/* -------------------------------------------------------------------- */
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ldr r3, =OSCR /* reset the OS Timer Count to zero */
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mov r2, #0
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str r2, [r3]
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ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
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/* so 0x300 should be plenty */
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1:
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ldr r2, [r3]
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cmp r4, r2
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bgt 1b
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cmp pc, #0xa0000000
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bls mem_init
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cmp pc, #0xb0000000
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bhi mem_init
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b skip_mem_init
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mem_init:
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ldr r1, =MDCNFG /* get memory controller base addr. */
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/* -------------------------------------------------------------------- */
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/* Step 2a: Initialize Asynchronous static memory controller */
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/* -------------------------------------------------------------------- */
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/* MSC registers: timing, bus width, mem type */
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/* MSC0: nCS(0,1) */
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ldr r2, =CONFIG_MSC0_VAL
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str r2, [r1, #MSC0_OFFSET]
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ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
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/* that data latches */
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/* MSC1: nCS(2,3) */
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ldr r2, =CONFIG_MSC1_VAL
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str r2, [r1, #MSC1_OFFSET]
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ldr r2, [r1, #MSC1_OFFSET]
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/* MSC2: nCS(4,5) */
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ldr r2, =CONFIG_MSC2_VAL
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str r2, [r1, #MSC2_OFFSET]
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ldr r2, [r1, #MSC2_OFFSET]
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/* -------------------------------------------------------------------- */
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/* Step 2b: Initialize Card Interface */
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/* -------------------------------------------------------------------- */
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/* MECR: Memory Expansion Card Register */
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ldr r2, =CONFIG_MECR_VAL
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str r2, [r1, #MECR_OFFSET]
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ldr r2, [r1, #MECR_OFFSET]
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/* MCMEM0: Card Interface slot 0 timing */
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ldr r2, =CONFIG_MCMEM0_VAL
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str r2, [r1, #MCMEM0_OFFSET]
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ldr r2, [r1, #MCMEM0_OFFSET]
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/* MCMEM1: Card Interface slot 1 timing */
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ldr r2, =CONFIG_MCMEM1_VAL
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str r2, [r1, #MCMEM1_OFFSET]
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ldr r2, [r1, #MCMEM1_OFFSET]
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/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
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ldr r2, =CONFIG_MCATT0_VAL
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str r2, [r1, #MCATT0_OFFSET]
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ldr r2, [r1, #MCATT0_OFFSET]
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/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
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ldr r2, =CONFIG_MCATT1_VAL
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str r2, [r1, #MCATT1_OFFSET]
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ldr r2, [r1, #MCATT1_OFFSET]
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/* MCIO0: Card Interface I/O Space Timing, slot 0 */
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ldr r2, =CONFIG_MCIO0_VAL
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str r2, [r1, #MCIO0_OFFSET]
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ldr r2, [r1, #MCIO0_OFFSET]
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/* MCIO1: Card Interface I/O Space Timing, slot 1 */
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ldr r2, =CONFIG_MCIO1_VAL
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str r2, [r1, #MCIO1_OFFSET]
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ldr r2, [r1, #MCIO1_OFFSET]
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/* -------------------------------------------------------------------- */
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/* Step 2c: Write FLYCNFG FIXME: what's that??? */
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/* -------------------------------------------------------------------- */
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ldr r2, =CONFIG_FLYCNFG_VAL
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str r2, [r1, #FLYCNFG_OFFSET]
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str r2, [r1, #FLYCNFG_OFFSET]
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/* -------------------------------------------------------------------- */
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/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
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/* -------------------------------------------------------------------- */
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/* Before accessing MDREFR we need a valid DRI field, so we set */
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/* this to power on defaults + DRI field. */
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ldr r4, [r1, #MDREFR_OFFSET]
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ldr r2, =0xFFF
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bic r4, r4, r2
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ldr r3, =CONFIG_MDREFR_VAL
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and r3, r3, r2
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orr r4, r4, r3
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str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
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orr r4, r4, #MDREFR_K0RUN
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orr r4, r4, #MDREFR_K0DB4
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orr r4, r4, #MDREFR_K0FREE
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orr r4, r4, #MDREFR_K2FREE
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orr r4, r4, #MDREFR_K0DB2
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orr r4, r4, #MDREFR_K1DB2
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bic r4, r4, #MDREFR_K1FREE
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str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
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ldr r4, [r1, #MDREFR_OFFSET]
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/* Note: preserve the mdrefr value in r4 */
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/* -------------------------------------------------------------------- */
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/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
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/* -------------------------------------------------------------------- */
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/* Initialize SXCNFG register. Assert the enable bits */
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/*
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* Write SXMRS to cause an MRS command to all enabled banks of
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* synchronous static memory. Note that SXLCR need not be
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* written at this time.
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*/
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ldr r2, =CONFIG_SXCNFG_VAL
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str r2, [r1, #SXCNFG_OFFSET]
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/* -------------------------------------------------------------------- */
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/* Step 4: Initialize SDRAM */
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/* -------------------------------------------------------------------- */
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bic r4, r4, #(MDREFR_K1FREE | MDREFR_K0FREE)
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orr r4, r4, #MDREFR_K1RUN
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orr r4, r4, #MDREFR_K2FREE
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bic r4, r4, #MDREFR_K2DB2
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str r4, [r1, #MDREFR_OFFSET]
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ldr r4, [r1, #MDREFR_OFFSET]
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bic r4, r4, #MDREFR_SLFRSH
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str r4, [r1, #MDREFR_OFFSET]
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ldr r4, [r1, #MDREFR_OFFSET]
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orr r4, r4, #MDREFR_E1PIN
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str r4, [r1, #MDREFR_OFFSET]
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ldr r4, [r1, #MDREFR_OFFSET]
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nop
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nop
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/*
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* Step 4d: write MDCNFG with MDCNFG:DEx deasserted
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* (set to 0), to configure but not enable each SDRAM
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* partition pair.
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*/
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ldr r4, =CONFIG_MDCNFG_VAL
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bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
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bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
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str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
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ldr r4, [r1, #MDCNFG_OFFSET]
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/*
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* Step 4e: Wait for the clock to the SDRAMs to stabilize,
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* 100..200 usec.
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*/
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ldr r3, =OSCR /* reset the OS Timer Count to zero */
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mov r2, #0
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str r2, [r3]
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ldr r4, =0x300 /* really 0x2E1 is about 200 usec, */
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/* so 0x300 should be plenty */
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1:
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ldr r2, [r3]
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cmp r4, r2
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bgt 1b
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/* Step 4f: Trigger a number (usually 8) refresh cycles by */
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/* attempting non-burst read or write accesses to disabled */
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/* SDRAM, as commonly specified in the power up sequence */
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/* documented in SDRAM data sheets. The address(es) used */
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/* for this purpose must not be cacheable. */
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ldr r3, =CONFIG_DRAM_BASE
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str r2, [r3]
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str r2, [r3]
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str r2, [r3]
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str r2, [r3]
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str r2, [r3]
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str r2, [r3]
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str r2, [r3]
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str r2, [r3]
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/*
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* Step 4g: Write MDCNFG with enable bits asserted
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* (MDCNFG:DEx set to 1)
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*/
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ldr r3, [r1, #MDCNFG_OFFSET]
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mov r4, r3
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orr r3, r3, #MDCNFG_DE0
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str r3, [r1, #MDCNFG_OFFSET]
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mov r0, r3
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/* Step 4h: Write MDMRS. */
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ldr r2, =CONFIG_MDMRS_VAL
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str r2, [r1, #MDMRS_OFFSET]
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/* enable APD */
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ldr r3, [r1, #MDREFR_OFFSET]
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orr r3, r3, #MDREFR_APD
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str r3, [r1, #MDREFR_OFFSET]
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/* We are finished with Intel's memory controller initialisation */
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skip_mem_init:
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wakeup:
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/* Are we waking from sleep? */
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ldr r0, =RCSR
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ldr r1, [r0]
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and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
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str r1, [r0]
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teq r1, #RCSR_SMR
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bne initirqs
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ldr r0, =PSSR
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mov r1, #PSSR_PH
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str r1, [r0]
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/* if so, resume at PSPR */
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ldr r0, =PSPR
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ldr r1, [r0]
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mov pc, r1
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/* -------------------------------------------------------------------- */
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/* Disable (mask) all interrupts at interrupt controller */
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/* -------------------------------------------------------------------- */
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initirqs:
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mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
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ldr r2, =ICLR
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str r1, [r2]
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ldr r2, =ICMR /* mask all interrupts at the controller */
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str r1, [r2]
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/* -------------------------------------------------------------------- */
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/* Clock initialisation */
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/* -------------------------------------------------------------------- */
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initclks:
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/* Disable the peripheral clocks, and set the core clock frequency */
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/* Turn Off on-chip peripheral clocks (except for memory) */
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/* for re-configuration. */
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ldr r1, =CKEN
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ldr r2, =CONFIG_CKEN
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str r2, [r1]
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/* ... and write the core clock config register */
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ldr r2, =CONFIG_CCCR
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ldr r1, =CCCR
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str r2, [r1]
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/* Turn on turbo mode */
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mrc p14, 0, r2, c6, c0, 0
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orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change */
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mcr p14, 0, r2, c6, c0, 0
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/* Re-write MDREFR */
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ldr r1, =MDCNFG
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ldr r2, [r1, #MDREFR_OFFSET]
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str r2, [r1, #MDREFR_OFFSET]
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/* enable the 32Khz oscillator for RTC and PowerManager */
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ldr r1, =OSCC
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mov r2, #OSCC_OON
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str r2, [r1]
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/* Interrupt init: Mask all interrupts */
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ldr r0, =ICMR /* enable no sources */
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mov r1, #0
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str r1, [r0]
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/* FIXME */
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#ifdef NODEBUG
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/* Disable software and data breakpoints */
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mov r0, #0
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mcr p15, 0, r0, c14, c8, 0 /* ibcr0 */
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mcr p15, 0, r0, c14, c9, 0 /* ibcr1 */
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mcr p15, 0, r0, c14, c4, 0 /* dbcon */
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/* Enable all debug functionality */
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mov r0, #0x80000000
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mcr p14, 0, r0, c10, c0, 0 /* dcsr */
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#endif
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/* -------------------------------------------------------------------- */
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/* End lowlevel_init */
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/* -------------------------------------------------------------------- */
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endlowlevel_init:
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mov pc, lr
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