250 lines
7.3 KiB
C
250 lines
7.3 KiB
C
/*
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* (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* Board support for Phytec's, i.MX31 based CPU card, called: PCM037
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <fs.h>
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#include <environment.h>
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#include <usb/ulpi.h>
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#include <mach/imx-regs.h>
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#include <mach/iomux-mx31.h>
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#include <asm/armlinux.h>
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#include <asm-generic/sections.h>
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#include <mach/gpio.h>
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#include <io.h>
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#include <asm/mmu.h>
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#include <partition.h>
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#include <generated/mach-types.h>
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#include <asm/barebox-arm.h>
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#include <mach/imx-nand.h>
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#include <mach/devices-imx31.h>
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#if defined CONFIG_PCM037_SDRAM_BANK0_128MB
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#define SDRAM0 128
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#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
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#define SDRAM0 256
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#endif
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#if defined CONFIG_PCM037_SDRAM_BANK1_128MB
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#define SDRAM1 128
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#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
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#define SDRAM1 256
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#endif
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struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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.flash_bbt = 1,
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};
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#ifdef CONFIG_USB
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static void pcm037_usb_init(void)
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{
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u32 tmp;
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/* enable clock */
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tmp = readl(0x53f80000);
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tmp |= (1 << 9);
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writel(tmp, 0x53f80000);
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/* Host 1 */
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tmp = readl(IMX_OTG_BASE + 0x600);
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tmp &= ~((3 << 21) | 1);
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tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20);
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writel(tmp, IMX_OTG_BASE + 0x600);
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tmp = readl(IMX_OTG_BASE + 0x184);
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tmp &= ~(3 << 30);
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tmp |= 2 << 30;
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writel(tmp, IMX_OTG_BASE + 0x184);
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imx_iomux_mode(MX31_PIN_USBOTG_DATA0__USBOTG_DATA0);
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imx_iomux_mode(MX31_PIN_USBOTG_DATA1__USBOTG_DATA1);
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imx_iomux_mode(MX31_PIN_USBOTG_DATA2__USBOTG_DATA2);
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imx_iomux_mode(MX31_PIN_USBOTG_DATA3__USBOTG_DATA3);
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imx_iomux_mode(MX31_PIN_USBOTG_DATA4__USBOTG_DATA4);
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imx_iomux_mode(MX31_PIN_USBOTG_DATA5__USBOTG_DATA5);
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imx_iomux_mode(MX31_PIN_USBOTG_DATA6__USBOTG_DATA6);
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imx_iomux_mode(MX31_PIN_USBOTG_DATA7__USBOTG_DATA7);
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imx_iomux_mode(MX31_PIN_USBOTG_CLK__USBOTG_CLK);
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imx_iomux_mode(MX31_PIN_USBOTG_DIR__USBOTG_DIR);
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imx_iomux_mode(MX31_PIN_USBOTG_NXT__USBOTG_NXT);
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imx_iomux_mode(MX31_PIN_USBOTG_STP__USBOTG_STP);
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mdelay(50);
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ulpi_setup((void *)(IMX_OTG_BASE + 0x170), 1);
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/* Host 2 */
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tmp = readl(IOMUXC_BASE + 0x8);
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tmp |= 1 << 11;
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writel(tmp, IOMUXC_BASE + 0x8);
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC));
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imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC));
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#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
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imx_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
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imx_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
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imx_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
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imx_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
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imx_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
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imx_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
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imx_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
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imx_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
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imx_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
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imx_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
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imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
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imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
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tmp = readl(IMX_OTG_BASE + 0x600);
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tmp &= ~((3 << 21) | 1);
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tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20);
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writel(tmp, IMX_OTG_BASE + 0x600);
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tmp = readl(IMX_OTG_BASE + 0x584);
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tmp &= ~(3 << 30);
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tmp |= 2 << 30;
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writel(tmp, IMX_OTG_BASE + 0x584);
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mdelay(50);
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ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1);
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/* Set to Host mode */
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tmp = readl(IMX_OTG_BASE + 0x1a8);
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writel(tmp | 0x3, IMX_OTG_BASE + 0x1a8);
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}
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#endif
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static int pcm037_mem_init(void)
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{
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arm_add_mem_device("ram0", IMX_SDRAM_CS0, SDRAM0 * 1024 * 1024);
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#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
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arm_add_mem_device("ram1", IMX_SDRAM_CS1, SDRAM1 * 1024 * 1024);
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#endif
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return 0;
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}
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mem_initcall(pcm037_mem_init);
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static int pcm037_mmu_init(void)
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{
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l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
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return 0;
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}
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postmmu_initcall(pcm037_mmu_init);
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static int imx31_devices_init(void)
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{
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__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
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__REG(CSCR_L(0)) = 0x10000d03;
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__REG(CSCR_A(0)) = 0x00720900;
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__REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */
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__REG(CSCR_L(1)) = 0x444a4541;
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__REG(CSCR_A(1)) = 0x44443302;
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__REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */
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__REG(CSCR_L(4)) = 0x22252521;
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__REG(CSCR_A(4)) = 0x22220a00;
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__REG(CSCR_U(5)) = 0x0000DCF6; /* CS5: SJA1000 */
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__REG(CSCR_L(5)) = 0x444A0301;
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__REG(CSCR_A(5)) = 0x44443302;
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/*
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* Up to 32MiB NOR type flash, connected to
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* CS line 0, data width is 16 bit
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*/
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add_cfi_flash_device(DEVICE_ID_DYNAMIC, IMX_CS0_BASE, 32 * 1024 * 1024, 0);
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/*
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* Create partitions that should be
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* not touched by any regular user
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*/
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devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); /* ourself */
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devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); /* environment */
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protect_file("/dev/env0", 1);
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/*
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* up to 2MiB static RAM type memory, connected
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* to CS4, data width is 16 bit
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*/
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add_mem_device("sram0", IMX_CS4_BASE, IMX_CS4_RANGE, /* area size */
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IORESOURCE_MEM_WRITEABLE);
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imx31_add_nand(&nand_info);
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/*
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* SMSC 9217 network controller
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* connected to CS line 1 and interrupt line
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* GPIO3, data width is 16 bit
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*/
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add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, IMX_CS1_BASE,
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IMX_CS1_RANGE, IORESOURCE_MEM, NULL);
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#ifdef CONFIG_USB
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pcm037_usb_init();
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add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE, NULL);
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add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
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#endif
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armlinux_set_bootparams((void *)0x80000100);
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armlinux_set_architecture(MACH_TYPE_PCM037);
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return 0;
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}
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device_initcall(imx31_devices_init);
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static int imx31_console_init(void)
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{
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/* init gpios for serial port */
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imx_iomux_mode(MX31_PIN_RXD1__RXD1);
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imx_iomux_mode(MX31_PIN_TXD1__TXD1);
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imx_iomux_mode(MX31_PIN_CTS1__CTS1);
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imx_iomux_mode(MX31_PIN_RTS1__RTS1);
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imx31_add_uart0();
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return 0;
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}
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console_initcall(imx31_console_init);
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#ifdef CONFIG_NAND_IMX_BOOT
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void __bare_init nand_boot(void)
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{
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imx_nand_load_image(_text, barebox_image_size);
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board_init_lowlevel_return();
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}
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#endif
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