348 lines
7.9 KiB
C
348 lines
7.9 KiB
C
/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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#include <common.h>
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#include <net.h>
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#include <init.h>
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#include <environment.h>
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#include <mach/imx-regs.h>
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#include <fec.h>
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#include <notifier.h>
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#include <mach/gpio.h>
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#include <asm/armlinux.h>
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#include <generated/mach-types.h>
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#include <partition.h>
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#include <fs.h>
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#include <nand.h>
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#include <spi/spi.h>
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#include <io.h>
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#include <mach/imx-nand.h>
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#include <mach/imx-pll.h>
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#include <mach/imxfb.h>
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#include <i2c/i2c.h>
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#include <mach/spi.h>
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#include <mach/iomux-mx27.h>
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#include <mach/devices-imx27.h>
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#include <mach/iim.h>
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#include <mfd/mc13xxx.h>
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#include "pll.h"
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static struct fec_platform_data fec_info = {
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.xcv_type = MII100,
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.phy_addr = 1,
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};
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static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
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static struct spi_imx_master pcm038_spi_0_data = {
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.chipselect = pcm038_spi_cs,
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.num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
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};
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static struct spi_board_info pcm038_spi_board_info[] = {
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{
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.name = "mc13xxx-spi",
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.bus_num = 0,
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.chip_select = 0,
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}
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};
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static struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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.flash_bbt = 1,
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};
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static struct imx_fb_videomode imxfb_mode = {
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.mode = {
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.name = "Sharp-LQ035Q7",
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.refresh = 60,
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.xres = 240,
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.yres = 320,
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.pixclock = 188679, /* in ps (5.3MHz) */
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.hsync_len = 7,
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.left_margin = 5,
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.right_margin = 16,
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.vsync_len = 1,
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.upper_margin = 7,
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.lower_margin = 9,
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},
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/*
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* - HSYNC active high
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* - VSYNC active high
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* - clk notenabled while idle
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* - clock not inverted
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* - data not inverted
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* - data enable low active
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* - enable sharp mode
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*/
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.pcr = 0xF00080C0,
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.bpp = 16,
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};
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static struct imx_fb_platform_data pcm038_fb_data = {
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.mode = &imxfb_mode,
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.num_modes = 1,
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.pwmr = 0x00A903FF,
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.lscr1 = 0x00120300,
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.dmacr = 0x00020010,
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};
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/**
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* The spctl0 register is a beast: Seems you can read it
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* only one times without writing it again.
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*/
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static inline uint32_t get_pll_spctl10(void)
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{
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uint32_t reg;
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reg = SPCTL0;
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SPCTL0 = reg;
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return reg;
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}
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/**
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* If the PLL settings are in place switch the CPU core frequency to the max. value
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*/
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static int pcm038_power_init(void)
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{
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uint32_t spctl0 = get_pll_spctl10();
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struct mc13xxx *mc13xxx = mc13xxx_get();
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/* PLL registers already set to their final values? */
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if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) {
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console_flush();
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if (mc13xxx) {
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mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0),
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MC13783_SWX_VOLTAGE(MC13783_SWX_VOLTAGE_1_450) |
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MC13783_SWX_VOLTAGE_DVS(MC13783_SWX_VOLTAGE_1_450) |
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MC13783_SWX_VOLTAGE_STANDBY(MC13783_SWX_VOLTAGE_1_450));
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mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(4),
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MC13783_SW1A_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) |
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MC13783_SW1A_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) |
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MC13783_SW1A_SOFTSTART |
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MC13783_SW1B_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) |
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MC13783_SW1B_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) |
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MC13783_SW1B_SOFTSTART |
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MC13783_SW_PLL_FACTOR(32));
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/* Setup VMMC voltage */
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if (IS_ENABLED(CONFIG_MCI_IMX)) {
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u32 val;
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mc13xxx_reg_read(mc13xxx, MC13783_REG_REG_SETTING(1), &val);
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/* VMMC1 = 3.00 V */
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val &= ~(7 << 6);
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val |= 6 << 6;
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mc13xxx_reg_write(mc13xxx, MC13783_REG_REG_SETTING(1), val);
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mc13xxx_reg_read(mc13xxx, MC13783_REG_REG_MODE(1), &val);
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/* Enable VMMC1 */
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val |= 1 << 18;
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mc13xxx_reg_write(mc13xxx, MC13783_REG_REG_MODE(1), val);
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}
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/* wait for required power level to run the CPU at 400 MHz */
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udelay(100000);
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CSCR = CSCR_VAL_FINAL;
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PCDR0 = 0x130410c3;
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PCDR1 = 0x09030911;
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/* Clocks have changed. Notify clients */
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clock_notifier_call_chain();
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} else {
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printf("Failed to initialize PMIC. Will continue with low CPU speed\n");
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}
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}
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/* clock gating enable */
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GPCR = 0x00050f08;
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return 0;
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}
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static int pcm038_mem_init(void)
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{
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arm_add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024);
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add_mem_device("ram1", 0xc8000000, 512 * 1024, /* Can be up to 2MiB */
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IORESOURCE_MEM_WRITEABLE);
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return 0;
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}
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mem_initcall(pcm038_mem_init);
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static int pcm038_devices_init(void)
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{
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int i;
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u64 uid = 0;
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char *envdev;
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unsigned int mode[] = {
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PD0_AIN_FEC_TXD0,
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PD1_AIN_FEC_TXD1,
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PD2_AIN_FEC_TXD2,
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PD3_AIN_FEC_TXD3,
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PD4_AOUT_FEC_RX_ER,
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PD5_AOUT_FEC_RXD1,
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PD6_AOUT_FEC_RXD2,
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PD7_AOUT_FEC_RXD3,
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PD8_AF_FEC_MDIO,
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PD9_AIN_FEC_MDC | GPIO_PUEN,
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PD10_AOUT_FEC_CRS,
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PD11_AOUT_FEC_TX_CLK,
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PD12_AOUT_FEC_RXD0,
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PD13_AOUT_FEC_RX_DV,
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PD14_AOUT_FEC_RX_CLK,
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PD15_AOUT_FEC_COL,
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PD16_AIN_FEC_TX_ER,
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PF23_AIN_FEC_TX_EN,
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PE12_PF_UART1_TXD,
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PE13_PF_UART1_RXD,
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PE14_PF_UART1_CTS,
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PE15_PF_UART1_RTS,
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PD25_PF_CSPI1_RDY,
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GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT,
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PD29_PF_CSPI1_SCLK,
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PD30_PF_CSPI1_MISO,
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PD31_PF_CSPI1_MOSI,
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/* display */
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PA5_PF_LSCLK,
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PA6_PF_LD0,
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PA7_PF_LD1,
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PA8_PF_LD2,
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PA9_PF_LD3,
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PA10_PF_LD4,
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PA11_PF_LD5,
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PA12_PF_LD6,
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PA13_PF_LD7,
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PA14_PF_LD8,
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PA15_PF_LD9,
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PA16_PF_LD10,
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PA17_PF_LD11,
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PA18_PF_LD12,
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PA19_PF_LD13,
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PA20_PF_LD14,
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PA21_PF_LD15,
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PA22_PF_LD16,
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PA23_PF_LD17,
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PA24_PF_REV,
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PA25_PF_CLS,
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PA26_PF_PS,
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PA27_PF_SPL_SPR,
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PA28_PF_HSYNC,
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PA29_PF_VSYNC,
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PA30_PF_CONTRAST,
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PA31_PF_OE_ACD,
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/* OTG host */
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PC7_PF_USBOTG_DATA5,
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PC8_PF_USBOTG_DATA6,
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PC9_PF_USBOTG_DATA0,
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PC10_PF_USBOTG_DATA2,
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PC11_PF_USBOTG_DATA1,
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PC12_PF_USBOTG_DATA4,
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PC13_PF_USBOTG_DATA3,
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PE0_PF_USBOTG_NXT,
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PE1_PF_USBOTG_STP,
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PE2_PF_USBOTG_DIR,
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PE24_PF_USBOTG_CLK,
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PE25_PF_USBOTG_DATA7,
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/* I2C1 */
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PD17_PF_I2C_DATA | GPIO_PUEN,
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PD18_PF_I2C_CLK,
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/* I2C2 */
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PC5_PF_I2C2_SDA,
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PC6_PF_I2C2_SCL,
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};
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/* configure 16 bit nor flash on cs0 */
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imx27_setup_weimcs(0, 0x22C2CF00, 0x75000D01, 0x00000900);
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/* configure SRAM on cs1 */
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imx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
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/* initizalize gpios */
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for (i = 0; i < ARRAY_SIZE(mode); i++)
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imx_gpio_mode(mode[i]);
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PCCR0 |= PCCR0_CSPI1_EN;
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PCCR1 |= PCCR1_PERCLK2_EN;
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spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
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imx27_add_spi0(&pcm038_spi_0_data);
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pcm038_power_init();
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add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0);
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imx27_add_nand(&nand_info);
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imx27_add_fb(&pcm038_fb_data);
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PCCR0 |= PCCR0_I2C1_EN | PCCR0_I2C2_EN;
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imx27_add_i2c0(NULL);
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imx27_add_i2c1(NULL);
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/* Register the fec device after the PLL re-initialisation
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* as the fec depends on the (now higher) ipg clock
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*/
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imx27_add_fec(&fec_info);
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switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
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case GPCR_BOOT_8BIT_NAND_2k:
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case GPCR_BOOT_16BIT_NAND_2k:
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case GPCR_BOOT_16BIT_NAND_512:
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case GPCR_BOOT_8BIT_NAND_512:
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devfs_add_partition("nand0", 0x00000, 0x80000,
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DEVFS_PARTITION_FIXED, "self_raw");
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dev_add_bb_dev("self_raw", "self0");
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devfs_add_partition("nand0", 0x80000, 0x100000,
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DEVFS_PARTITION_FIXED, "env_raw");
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dev_add_bb_dev("env_raw", "env0");
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envdev = "NAND";
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break;
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default:
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devfs_add_partition("nor0", 0x00000, 0x80000,
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DEVFS_PARTITION_FIXED, "self0");
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devfs_add_partition("nor0", 0x80000, 0x100000,
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DEVFS_PARTITION_FIXED, "env0");
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protect_file("/dev/env0", 1);
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envdev = "NOR";
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}
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printf("Using environment in %s Flash\n", envdev);
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if (imx_iim_read(1, 1, &uid, 6) == 6)
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armlinux_set_serial(uid);
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armlinux_set_bootparams((void *)0xa0000100);
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armlinux_set_architecture(MACH_TYPE_PCM038);
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return 0;
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}
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device_initcall(pcm038_devices_init);
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static int pcm038_console_init(void)
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{
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imx27_add_uart0();
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return 0;
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}
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console_initcall(pcm038_console_init);
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