143 lines
4.3 KiB
C
143 lines
4.3 KiB
C
/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (c) 2016 Alexander Kurz <akurz@blala.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <mach/imx35-regs.h>
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#include <mach/imx-pll.h>
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#include <mach/esdctl.h>
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#include <asm/cache-l2x0.h>
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#include <io.h>
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#include <mach/imx-nand.h>
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#include <asm/barebox-arm.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/sections.h>
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#include <asm-generic/memory_layout.h>
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#include <asm/system.h>
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void __bare_init __naked barebox_arm_reset_vector(void)
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{
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uint32_t r, s;
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unsigned long ccm_base = MX35_CCM_BASE_ADDR;
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register uint32_t loops = 0x20000;
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arm_cpu_lowlevel_init();
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arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
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r = get_cr();
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r |= CR_Z; /* Flow prediction (Z) */
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r |= CR_U; /* unaligned accesses */
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r |= CR_FI; /* Low Int Latency */
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__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r"(s));
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s |= 0x7;
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__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s));
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set_cr(r);
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r = 0;
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__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
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/*
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* Branch predicition is now enabled. Flush the BTAC to ensure a valid
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* starting point. Don't flush BTAC while it is disabled to avoid
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* ARM1136 erratum 408023.
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*/
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__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r));
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/* invalidate I cache and D cache */
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__asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r));
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/* invalidate TLBs */
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__asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r));
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/* Drain the write buffer */
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__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r));
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/* Also setup the Peripheral Port Remap register inside the core */
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r = 0x40000015; /* start from AIPS 2GB region */
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__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
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/*
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* End of ARM1136 init
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*/
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writel(0x003F4208, ccm_base + MX35_CCM_CCMR);
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/* Set MPLL , arm clock and ahb clock*/
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writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL);
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writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL);
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writel(0x00001000, ccm_base + MX35_CCM_PDR0);
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r = readl(ccm_base + MX35_CCM_CGR0);
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r |= 0x3 << MX35_CCM_CGR0_CSPI1_SHIFT;
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r |= 0x3 << MX35_CCM_CGR0_EPIT1_SHIFT;
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r |= 0x3 << MX35_CCM_CGR0_ESDHC1_SHIFT;
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writel(r, ccm_base + MX35_CCM_CGR0);
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r = readl(ccm_base + MX35_CCM_CGR1);
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r |= 0x3 << MX35_CCM_CGR1_IOMUX_SHIFT;
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r |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT;
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r |= 0x3 << MX35_CCM_CGR1_I2C2_SHIFT;
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r |= 0x3 << MX35_CCM_CGR1_GPIO1_SHIFT;
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r |= 0x3 << MX35_CCM_CGR1_GPIO2_SHIFT;
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writel(r, ccm_base + MX35_CCM_CGR1);
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r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
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r |= 0x1000;
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writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL);
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/* Skip SDRAM initialization if we run from RAM */
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r = get_pc();
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if (r > 0x80000000 && r < 0x90000000)
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goto out;
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/* Init Mobile DDR */
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writel(0x0000000E, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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/* ESD_MISC: Enable DDR SDRAM */
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writel(0x00000004, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b" : "=r" (loops) : "0" (loops));
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writel(0x0019672f, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
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/* ESD_ESDCTL0 : select Prechare-All mode */
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writel(0x93220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400);
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/* ESD_ESDCTL0: Auto Refresh command */
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writel(0xA3220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writeb(0xda, MX35_CSD0_BASE_ADDR);
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writeb(0xda, MX35_CSD0_BASE_ADDR);
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/* ESD_ESDCTL0: Load Mode Register */
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writel(0xB3220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33);
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writeb(0xff, MX35_CSD0_BASE_ADDR + 0x2000000);
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/* ESD_ESDCTL0: enable Auto-Refresh */
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writel(0x83228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writel(0x0000000c, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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writel(0xdeadbeef, MX35_CSD0_BASE_ADDR);
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writel(0x00e78000, MX35_CSD0_BASE_ADDR + 0x1030);
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out:
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imx35_barebox_entry(NULL);
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}
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