265 lines
7.2 KiB
C
265 lines
7.2 KiB
C
#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <linux/sizes.h>
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#include <mach/pxa-regs.h>
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#include <mach/regs-ost.h>
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/*
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* Memory settings
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*/
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#define DEFAULT_MSC0_VAL 0x23F2B8F2
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#define DEFAULT_MSC1_VAL 0x7ff0fff1
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/*
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* MSC2: static partitions 4 and 5
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*
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* [31] 0 - RBUFF5
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* [30:28] 111 - RRR5
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* [27:24] 1111- RDN5
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* [23:20] 1111- RDF5
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* [19] 0 - RBW5
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* [18:16] 000 - RT5
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* [15] 0 - RBUFF4: Slow device (don't wait for data return)
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* [14:12] 111 - RRR4: Toff=(2*RRR + 1)*CLK_MEM (from nCS=1 to next nCS=0)
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* [11:8] 1111- RDN4: T=2*RDN*CLK_MEM (from nOE=1 to addr hold)
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* [7:4] 1111- RDF4: T=RDF*CLK_MEM of hold nOE/nPWE for read/write
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* [3] 0 - RBW4: Bus width is 32 bits
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* [2:0] 000 - RT4: Partition is VLIO
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*/
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#define DEFAULT_MSC2_VAL 0x7ff0fff4
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/*
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* MDCNFG: SDRAM Configuration Register
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*
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* [31] 0 - Memory map 0/1 uses normal 256 MBytes
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* [30] 0 - dcacx2: no extra column addressing
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* [29] 0 - reserved
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* [28] 0 - SA1111 compatiblity mode
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* [27] 0 - latch return data with return clock
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* [26] 0 - alternate addressing for pair 2/3
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* [25:24] 00 - timings
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* [23] 0 - internal banks in lower partition 2/3 (not used)
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* [22:21] 00 - row address bits for partition 2/3 (not used)
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* [20:19] 00 - column address bits for partition 2/3 (not used)
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* [18] 0 - SDRAM partition 2/3 width is 32 bit
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* [17] 0 - SDRAM partition 3 disabled
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* [16] 0 - SDRAM partition 2 disabled
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* [15] 0 - Stack1 : see stack0
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* [14] 0 - dcacx0 : no extra column addressing
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* [13] 0 - stack0 : stack = 0b00 => SDRAM address placed on MA<24:10>
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* [12] 0 - SA1110 compatiblity mode
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* [11] 1 - always 1
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* [10] 0 - no alternate addressing for pair 0/1
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* [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=7*MemClk tRC=11*MemClk
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* [7] 1 - 4 internal banks in partitions 0/1
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* [06:05] 10 - drac0: 13 row address bits for partition 0/1
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* [04:03] 01 - dcac0: 9 column address bits for partition 0/1
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* [02] 0 - SDRAM partition 0/1 width is 32 bit
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* [01] 1 - enable SDRAM partition 1
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* [00] 1 - enable SDRAM partition 0
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*
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* Configuration is for 1 bank of 64MBytes (13 rows * 9 cols)
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* in bank0, of width 32 bits, with 4 internal banks.
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* Timings (in times of SDCLK<1>): tRP = 3clk, CL=3, rRCD=3clk,
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* tRAS=7clk, tRC=11clk
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*/
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#define DEFAULT_MDCNFG_VAL 0x00000acb
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/*
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* MDREFR: SDRAM Configuration Register
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*
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* [25] 0 - K2FREE=0
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* [24] 0 - K1FREE=0
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* [23] 0 - K0FREE=0
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* [22] 0 - SLFRSH=0
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* [21]
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* [20] 0 - APD
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* [19] 0 - K2DB2=0
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* [18] 0 - K2RUN=0
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* [17] 1 - K1DB2=1
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* [16] 1 - K1RUN=1
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* [15] 0 - EP1IN
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* [14] 1 - K0DB2=1
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* [13] 1 - K0RUN=1
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* [12]
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* [11..0] 17 - DRI=17
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*/
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#define DEFAULT_MDREFR_VAL 0x00036017
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#define DEFAULT_MDMRS_VAL 0x00320032
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#define DEFAULT_FLYCNFG_VAL 0x00000000
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#define DEFAULT_SXCNFG_VAL 0x40044004
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/*
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* PCMCIA and CF Interfaces
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*/
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#define DEFAULT_MECR_VAL 0x00000001
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#define DEFAULT_MCMEM0_VAL 0x00014307
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#define DEFAULT_MCMEM1_VAL 0x00014307
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#define DEFAULT_MCATT0_VAL 0x0001c787
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#define DEFAULT_MCATT1_VAL 0x0001c787
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#define DEFAULT_MCIO0_VAL 0x0001430f
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#define DEFAULT_MCIO1_VAL 0x0001430f
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static inline void writelrb(uint32_t val, volatile u32 __iomem *addr)
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{
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writel(val, addr);
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barrier();
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readl(addr);
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barrier();
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}
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static inline void pxa_wait_ticks(int ticks)
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{
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writel(0, &OSCR);
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while (readl(&OSCR) < ticks)
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barrier();
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}
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static inline void pxa2xx_dram_init(void)
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{
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uint32_t tmp, mask;
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int i;
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/*
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* 1) Initialize Asynchronous static memory controller
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*/
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writelrb(DEFAULT_MSC1_VAL, &MSC1);
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writelrb(DEFAULT_MSC2_VAL, &MSC2);
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/*
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* 2) Initialize Card Interface
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*/
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/* MECR: Memory Expansion Card Register */
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writelrb(DEFAULT_MECR_VAL, &MECR);
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/* MCMEM0: Card Interface slot 0 timing */
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writelrb(DEFAULT_MCMEM0_VAL, &MCMEM0);
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/* MCMEM1: Card Interface slot 1 timing */
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writelrb(DEFAULT_MCMEM1_VAL, &MCMEM1);
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/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
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writelrb(DEFAULT_MCATT0_VAL, &MCATT0);
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/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
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writelrb(DEFAULT_MCATT1_VAL, &MCATT1);
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/* MCIO0: Card Interface I/O Space Timing, slot 0 */
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writelrb(DEFAULT_MCIO0_VAL, &MCIO0);
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/* MCIO1: Card Interface I/O Space Timing, slot 1 */
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writelrb(DEFAULT_MCIO1_VAL, &MCIO1);
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/*
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* 3) Configure Fly-By DMA register
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*/
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writelrb(DEFAULT_FLYCNFG_VAL, &FLYCNFG);
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/*
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* 4) Initialize Timing for Sync Memory (SDCLK0)
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*/
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/*
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* Before accessing MDREFR we need a valid DRI field, so we set
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* this to power on defaults + DRI field.
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*/
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/* Read current MDREFR config and zero out DRI */
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tmp = readl(&MDREFR) & ~0xfff;
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tmp |= DEFAULT_MDREFR_VAL & 0xfff;
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writelrb(tmp, &MDREFR);
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/* clear the free-running clock bits (clear K0Free, K1Free, K2Free) */
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mask = MDREFR_K0FREE | MDREFR_K1FREE | MDREFR_K2FREE |
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MDREFR_K0DB2 | MDREFR_K0DB4 | MDREFR_K1DB2 | MDREFR_K2DB2 |
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MDREFR_K0RUN | MDREFR_K1RUN | MDREFR_K2RUN;
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tmp &= ~mask;
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tmp |= (DEFAULT_MDREFR_VAL & mask);
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writelrb(tmp, &MDREFR);
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/*
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* 5) Initialize Synchronous Static Memory (Flash/Peripherals)
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*/
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/* Initialize SXCNFG register. Assert the enable bits.
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*
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* Write SXMRS to cause an MRS command to all enabled banks of
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* synchronous static memory. Note that SXLCR need not be written
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* at this time.
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*/
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writelrb(DEFAULT_SXCNFG_VAL, &SXCNFG);
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/*
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* 6) Initialize SDRAM
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*/
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tmp &= ~MDREFR_SLFRSH;
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writelrb(tmp, &MDREFR);
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tmp |= MDREFR_E1PIN;
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writelrb(tmp, &MDREFR);
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/*
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* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
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* but not enable each SDRAM partition pair.
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*/
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mask = MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3;
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writelrb(DEFAULT_MDCNFG_VAL & ~mask, &MDCNFG);
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/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
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pxa_wait_ticks(0x300);
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/*
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* 8) Trigger a number (usually 8) refresh cycles by attempting
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* non-burst read or write accesses to disabled SDRAM, as commonly
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* specified in the power up sequence documented in SDRAM data
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* sheets. The address(es) used for this purpose must not be
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* cacheable.
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*/
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for (i = 9; i >= 0; i--) {
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readl(0xa0000000);
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barrier();
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}
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/*
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* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
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*/
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tmp = (readl(&MDCNFG) & ~mask) | (DEFAULT_MDCNFG_VAL & mask);
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writelrb(tmp, &MDCNFG);
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/*
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* 10) Write MDMRS.
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*/
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writelrb(DEFAULT_MDMRS_VAL, &MDMRS);
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/*
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* 11) Enable APD
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*/
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if (DEFAULT_MDREFR_VAL & MDREFR_APD) {
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tmp = readl(&MDREFR);
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tmp |= MDREFR_APD;
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writelrb(tmp, &MDREFR);
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}
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}
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void __bare_init __naked barebox_arm_reset_vector(void)
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{
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unsigned long pssr = PSPR;
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unsigned long pc = get_pc();
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arm_cpu_lowlevel_init();
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CKEN |= CKEN_OSTIMER | CKEN_MEMC | CKEN_FFUART;
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/*
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* When not running from SDRAM, get it out of self refresh, and/or
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* initialize it.
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*/
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if (!(pc >= 0xa0000000 && pc < 0xb0000000))
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pxa2xx_dram_init();
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if ((pssr >= 0xa0000000 && pssr < 0xb0000000) ||
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(pssr >= 0x04000000 && pssr < 0x10000000))
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asm("mov pc, %0" : : "r"(pssr) : );
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barebox_arm_entry(0xa0000000, SZ_64M, 0);
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}
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