146 lines
4.7 KiB
C
146 lines
4.7 KiB
C
/*
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* Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <linux/sizes.h>
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#include <io.h>
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#include <init.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <mach/am33xx-silicon.h>
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#include <mach/am33xx-clock.h>
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#include <mach/generic.h>
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#include <mach/sdrc.h>
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#include <mach/sys_info.h>
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#include <mach/syslib.h>
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#include <mach/am33xx-mux.h>
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#include <mach/am33xx-generic.h>
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#include <mach/wdt.h>
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#include <debug_ll.h>
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#include "ram-timings.h"
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#define CLK_M_OSC_MHZ 25
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#define DDR_IOCTRL 0x18B
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static const struct am33xx_cmd_control physom_cmd = {
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.slave_ratio0 = 0x80,
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.dll_lock_diff0 = 0x0,
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.invert_clkout0 = 0x0,
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.slave_ratio1 = 0x80,
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.dll_lock_diff1 = 0x0,
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.invert_clkout1 = 0x0,
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.slave_ratio2 = 0x80,
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.dll_lock_diff2 = 0x0,
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.invert_clkout2 = 0x0,
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};
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/**
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* @brief The basic entry point for board initialization.
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*
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* This is called as part of machine init (after arch init).
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* This is again called with stack in SRAM, so not too many
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* constructs possible here.
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*
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* @return void
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*/
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static noinline void physom_board_init(int sdram, void *fdt)
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{
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struct am335x_sdram_timings *timing = &physom_timings[sdram];
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/*
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* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
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while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
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while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
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am33xx_pll_init(MPUPLL_M_600, CLK_M_OSC_MHZ, DDRPLL_M_400);
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am335x_sdram_init(DDR_IOCTRL, &physom_cmd,
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&timing->regs,
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&timing->data);
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am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE);
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am33xx_enable_uart0_pin_mux();
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omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
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putc_ll('>');
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am335x_barebox_entry(fdt);
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}
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static noinline void physom_board_entry(unsigned long bootinfo, int sdram, void *fdt)
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{
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am33xx_save_bootinfo((void *)bootinfo);
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arm_cpu_lowlevel_init();
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/*
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* Setup C environment, the board init code uses global variables.
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* Stackpointer has already been initialized by the ROM code.
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*/
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relocate_to_current_adr();
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setup_c();
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physom_board_init(sdram, fdt);
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}
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#define PHYTEC_ENTRY_MLO(name, fdt_name, sdram) \
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ENTRY_FUNCTION(name, bootinfo, r1, r2) \
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{ \
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extern char __dtb_##fdt_name##_start[]; \
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void *fdt =__dtb_##fdt_name##_start - \
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get_runtime_offset(); \
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physom_board_entry(bootinfo, sdram, fdt); \
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}
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#define PHYTEC_ENTRY(name, fdt_name) \
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ENTRY_FUNCTION(name, r0, r1, r2) \
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{ \
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extern char __dtb_##fdt_name##_start[]; \
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void *fdt =__dtb_##fdt_name##_start - \
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get_runtime_offset(); \
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am335x_barebox_entry(fdt); \
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}
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/* phycore-som */
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PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_128mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J64M1615IT_128MB);
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PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_256mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J128M16125IT_256MB);
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PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J256M16HA15EIT_512MB);
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PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_2x512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J512M8125IT_2x512MB);
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PHYTEC_ENTRY(start_am33xx_phytec_phycore_sdram, am335x_phytec_phycore_som);
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PHYTEC_ENTRY(start_am33xx_phytec_phycore_no_spi_sdram, am335x_phytec_phycore_som_no_spi);
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/* phyflex-som */
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PHYTEC_ENTRY_MLO(start_am33xx_phytec_phyflex_sram_256mb, am335x_phytec_phyflex_som_mlo, PHYFLEX_MT41K128M16JT_256MB);
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PHYTEC_ENTRY_MLO(start_am33xx_phytec_phyflex_sram_512mb, am335x_phytec_phyflex_som_mlo, PHYFLEX_MT41K256M16HA_512MB);
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PHYTEC_ENTRY(start_am33xx_phytec_phyflex_sdram, am335x_phytec_phyflex_som);
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/* phycard-som */
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PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycard_sram_256mb, am335x_phytec_phycard_som_mlo, PHYCARD_NT5CB128M16BP_256MB);
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PHYTEC_ENTRY(start_am33xx_phytec_phycard_sdram, am335x_phytec_phycard_som);
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/* sysmocom-odu */
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PHYTEC_ENTRY_MLO(start_am33xx_sysmocom_odu_sram, am335x_sysmocom_odu, PHYCARD_NT5CB128M16BP_256MB);
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PHYTEC_ENTRY(start_am33xx_sysmocom_odu_sdram, am335x_sysmocom_odu);
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/* gsmk-owhw */
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PHYTEC_ENTRY_MLO(start_am33xx_gsmk_owhw_sram, am335x_gsmk_owhw, PHYCARD_NT5CB128M16BP_256MB);
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PHYTEC_ENTRY(start_am33xx_gsmk_owhw_sdram, am335x_gsmk_owhw);
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