253 lines
7.2 KiB
C
253 lines
7.2 KiB
C
/*
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* Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de>
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*
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* Partly based on code (C) Copyright 2010-2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <mach/lowlevel.h>
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#include <mach/tegra20-car.h>
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#include <mach/tegra20-pmc.h>
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#include <mach/tegra30-car.h>
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#include <mach/tegra30-flow.h>
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/* instruct the PMIC to enable the CPU power rail */
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static void enable_maincomplex_powerrail(void)
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{
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u32 reg;
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reg = readl(TEGRA_PMC_BASE + PMC_CNTRL);
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reg |= PMC_CNTRL_CPUPWRREQ_OE;
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writel(reg, TEGRA_PMC_BASE);
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}
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/* put every core in the main CPU complex into reset state */
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static void assert_maincomplex_reset(int num_cores)
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{
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u32 mask = 0;
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int i;
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for (i = 0; i < num_cores; i++)
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mask |= 0x1111 << i;
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writel(mask, TEGRA_CLK_RESET_BASE + CRC_RST_CPU_CMPLX_SET);
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writel(CRC_RST_DEV_L_CPU, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_SET);
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}
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/* release reset state of the first core of the main CPU complex */
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static void deassert_cpu0_reset(void)
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{
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writel(0x1111, TEGRA_CLK_RESET_BASE + CRC_RST_CPU_CMPLX_CLR);
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writel(CRC_RST_DEV_L_CPU, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_CLR);
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}
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/* stop all internal and external clocks to the main CPU complex */
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static void stop_maincomplex_clocks(int num_cores)
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{
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u32 reg;
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int i;
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reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX);
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for (i = 0; i < num_cores; i++)
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reg |= 0x1 << (8 + i);
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writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX);
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reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_L);
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reg &= ~CRC_CLK_OUT_ENB_L_CPU;
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writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_L);
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}
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struct pll_config {
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u16 divn;
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u16 divm;
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u16 divp;
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u16 cpcon;
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};
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static struct pll_config pllx_config_table[][4] = {
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{
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{1000, 13, 0, 12}, /* OSC 13.0 MHz */
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{625, 12, 0, 8 }, /* OSC 19.2 MHz */
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{1000, 12, 0, 12}, /* OSC 12.0 MHz */
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{1000, 26, 0, 12}, /* OSC 26.0 MHz */
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}, /* TEGRA 20 */
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{
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{862, 8, 0, 8},
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{583, 8, 0, 4},
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{700, 6, 0, 8},
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{700, 13, 0, 8},
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}, /* TEGRA 30 */
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};
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static void init_pllx(void)
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{
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struct pll_config *conf;
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enum tegra_chiptype chiptype;
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u8 osc_freq;
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u32 reg;
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/* If PLLX is already enabled, just return */
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if (readl(TEGRA_CLK_RESET_BASE + CRC_PLLX_BASE) & CRC_PLLX_BASE_ENABLE)
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return;
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chiptype = tegra_get_chiptype();
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osc_freq = (readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL) &
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CRC_OSC_CTRL_OSC_FREQ_MASK) >> CRC_OSC_CTRL_OSC_FREQ_SHIFT;
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conf = &pllx_config_table[chiptype][osc_freq];
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/* we are not relocated yet - globals are a bit more tricky here */
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conf = (struct pll_config *)((char *)conf - get_runtime_offset());
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/* set PLL bypass and frequency parameters */
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reg = CRC_PLLX_BASE_BYPASS;
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reg |= (conf->divm << CRC_PLLX_BASE_DIVM_SHIFT) &
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CRC_PLLX_BASE_DIVM_MASK;
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reg |= (conf->divn << CRC_PLLX_BASE_DIVN_SHIFT) &
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CRC_PLLX_BASE_DIVN_MASK;
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reg |= (conf->divp << CRC_PLLX_BASE_DIVP_SHIFT) &
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CRC_PLLX_BASE_DIVP_MASK;
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writel(reg, TEGRA_CLK_RESET_BASE + CRC_PLLX_BASE);
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/* set chargepump parameters */
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reg = (conf->cpcon << CRC_PLLX_MISC_CPCON_SHIFT) &
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CRC_PLLX_MISC_CPCON_MASK;
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if (conf->divn > 600)
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reg |= CRC_PLLX_MISC_DCCON;
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writel(reg, TEGRA_CLK_RESET_BASE + CRC_PLLX_MISC);
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/* enable PLL and disable bypass */
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reg = readl(TEGRA_CLK_RESET_BASE + CRC_PLLX_BASE);
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reg |= CRC_PLLX_BASE_ENABLE;
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reg &= ~CRC_PLLX_BASE_BYPASS;
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writel(reg, TEGRA_CLK_RESET_BASE + CRC_PLLX_BASE);
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/* enable PLL lock */
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reg = readl(TEGRA_CLK_RESET_BASE + CRC_PLLX_MISC);
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reg |= CRC_PLLX_MISC_LOCK_ENABLE;
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writel(reg, TEGRA_CLK_RESET_BASE + CRC_PLLX_MISC);
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}
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/* start internal and external clocks to core 0 of the main CPU complex */
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static void start_cpu0_clocks(void)
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{
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u32 reg;
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/* setup PLLX */
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init_pllx();
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/* setup super CLK */
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writel(CRC_SCLK_BURST_POLICY_SYS_STATE_RUN <<
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CRC_SCLK_BURST_POLICY_SYS_STATE_SHIFT,
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TEGRA_CLK_RESET_BASE + CRC_SCLK_BURST_POLICY);
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writel(CRC_SUPER_SDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_SCLK_DIV);
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writel(1 << CRC_CLK_SYSTEM_RATE_AHB_SHIFT,
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TEGRA_CLK_RESET_BASE + CRC_CLK_SYSTEM_RATE);
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if (tegra_get_chiptype() >= TEGRA30) {
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/* init MSELECT */
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writel(CRC_RST_DEV_V_MSELECT,
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TEGRA_CLK_RESET_BASE + CRC_RST_DEV_V_SET);
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writel((CRC_CLK_SOURCE_MSEL_SRC_CLKM <<
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CRC_CLK_SOURCE_MSEL_SRC_SHIFT),
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TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_MSEL);
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writel(CRC_CLK_OUT_ENB_V_MSELECT,
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TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_V);
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tegra_ll_delay_usec(3);
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writel(CRC_RST_DEV_V_MSELECT,
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TEGRA_CLK_RESET_BASE + CRC_RST_DEV_V_CLR);
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}
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/* deassert clock stop for cpu 0 */
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reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX);
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reg &= ~CRC_CLK_CPU_CMPLX_CPU0_CLK_STP;
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writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX);
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/* enable main CPU complex clock */
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reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_L);
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reg |= CRC_CLK_OUT_ENB_L_CPU;
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writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_L);
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/* give clocks some time to settle */
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tegra_ll_delay_usec(300);
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}
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static void maincomplex_powerup(void)
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{
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u32 reg;
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if (!(readl(TEGRA_PMC_BASE + PMC_PWRGATE_STATUS) &
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PMC_PWRGATE_STATUS_CPU)) {
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writel(PMC_PWRGATE_TOGGLE_START | PMC_PWRGATE_TOGGLE_PARTID_CPU,
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TEGRA_PMC_BASE + PMC_PWRGATE_TOGGLE);
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while (!(readl(TEGRA_PMC_BASE + PMC_PWRGATE_STATUS) &
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PMC_PWRGATE_STATUS_CPU));
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reg = readl(TEGRA_PMC_BASE + PMC_REMOVE_CLAMPING_CMD);
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reg |= PMC_REMOVE_CLAMPING_CMD_CPU;
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writel(reg, TEGRA_PMC_BASE + PMC_REMOVE_CLAMPING_CMD);
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tegra_ll_delay_usec(1000);
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}
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}
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static void tegra_cluster_switch_hp(void)
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{
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u32 reg;
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reg = readl(TEGRA_FLOW_CTRL_BASE + FLOW_CLUSTER_CONTROL);
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reg &= ~FLOW_CLUSTER_CONTROL_ACTIVE_LP;
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writel(reg, TEGRA_FLOW_CTRL_BASE + FLOW_CLUSTER_CONTROL);
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}
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void tegra_avp_reset_vector(uint32_t boarddata)
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{
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int num_cores;
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/* we want to bring up the high performance CPU complex */
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if (tegra_get_chiptype() == TEGRA30)
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tegra_cluster_switch_hp();
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/* get the number of cores in the main CPU complex of the current SoC */
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num_cores = tegra_get_num_cores();
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/* bring down main CPU complex (this may be a warm boot) */
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enable_maincomplex_powerrail();
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assert_maincomplex_reset(num_cores);
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stop_maincomplex_clocks(num_cores);
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/* set start address for the main CPU complex processors */
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writel(tegra_maincomplex_entry - get_runtime_offset(),
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TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
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/* put boarddata in scratch reg, for main CPU to fetch after startup */
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writel(boarddata, TEGRA_PMC_BASE + PMC_SCRATCH(10));
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/* bring up main CPU complex */
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start_cpu0_clocks();
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maincomplex_powerup();
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deassert_cpu0_reset();
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/* assert AVP reset to stop execution here */
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writel(CRC_RST_DEV_L_COP, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_SET);
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unreachable();
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}
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