312 lines
6.5 KiB
C
312 lines
6.5 KiB
C
#include <common.h>
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#include <io.h>
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#include <asm-generic/div64.h>
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#include <asm-generic/errno.h>
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#include <mach/imx51-regs.h>
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#include <mach/clock.h>
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#include <mach/clock-imx51_53.h>
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static u32 ccm_readl(u32 ofs)
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{
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return readl(IOMEM(MX51_CCM_BASE_ADDR) + ofs);
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}
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static void ccm_writel(u32 val, u32 ofs)
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{
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writel(val, MX51_CCM_BASE_ADDR + ofs);
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}
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static unsigned long ckil_get_rate(void)
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{
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return 32768;
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}
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static unsigned long osc_get_rate(void)
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{
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return 24000000;
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}
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static unsigned long fpm_get_rate(void)
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{
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return ckil_get_rate() * 512;
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}
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static unsigned long lp_apm_get_rate(void)
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{
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if (ccm_readl(MX5_CCM_CCSR) & MX5_CCM_CCSR_LP_APM_SEL)
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return fpm_get_rate();
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else
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return osc_get_rate();
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}
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static unsigned long pll_get_rate(void __iomem *pllbase)
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{
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long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
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unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
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u64 temp;
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unsigned long parent_rate;
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dp_ctl = readl(pllbase + MX5_PLL_DP_CTL);
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if ((dp_ctl & MX5_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
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parent_rate = fpm_get_rate();
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else
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parent_rate = osc_get_rate();
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pll_hfsm = dp_ctl & MX5_PLL_DP_CTL_HFSM;
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dbl = dp_ctl & MX5_PLL_DP_CTL_DPDCK0_2_EN;
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if (pll_hfsm == 0) {
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dp_op = readl(pllbase + MX5_PLL_DP_OP);
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dp_mfd = readl(pllbase + MX5_PLL_DP_MFD);
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dp_mfn = readl(pllbase + MX5_PLL_DP_MFN);
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} else {
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dp_op = readl(pllbase + MX5_PLL_DP_HFS_OP);
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dp_mfd = readl(pllbase + MX5_PLL_DP_HFS_MFD);
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dp_mfn = readl(pllbase + MX5_PLL_DP_HFS_MFN);
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}
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pdf = dp_op & MX5_PLL_DP_OP_PDF_MASK;
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mfi = (dp_op & MX5_PLL_DP_OP_MFI_MASK) >> MX5_PLL_DP_OP_MFI_OFFSET;
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mfi = (mfi <= 5) ? 5 : mfi;
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mfd = dp_mfd & MX5_PLL_DP_MFD_MASK;
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mfn = mfn_abs = dp_mfn & MX5_PLL_DP_MFN_MASK;
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/* Sign extend to 32-bits */
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if (mfn >= 0x04000000) {
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mfn |= 0xFC000000;
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mfn_abs = -mfn;
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}
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ref_clk = 2 * parent_rate;
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if (dbl != 0)
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ref_clk *= 2;
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ref_clk /= (pdf + 1);
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temp = (u64)ref_clk * mfn_abs;
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do_div(temp, mfd + 1);
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if (mfn < 0)
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temp = -temp;
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temp = (ref_clk * mfi) + temp;
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return temp;
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}
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static unsigned long pll1_main_get_rate(void)
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{
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return pll_get_rate((void __iomem *)MX51_PLL1_BASE_ADDR);
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}
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static unsigned long pll2_sw_get_rate(void)
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{
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return pll_get_rate((void __iomem *)MX51_PLL2_BASE_ADDR);
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}
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static unsigned long pll3_sw_get_rate(void)
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{
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return pll_get_rate((void __iomem *)MX51_PLL3_BASE_ADDR);
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}
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static unsigned long get_rate_select(int select,
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unsigned long (* get_rate1)(void),
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unsigned long (* get_rate2)(void),
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unsigned long (* get_rate3)(void),
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unsigned long (* get_rate4)(void))
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{
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switch (select) {
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case 0:
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return get_rate1 ? get_rate1() : 0;
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case 1:
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return get_rate2 ? get_rate2() : 0;
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case 2:
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return get_rate3 ? get_rate3() : 0;
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case 3:
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return get_rate4 ? get_rate4() : 0;
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}
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return 0;
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}
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unsigned long imx_get_uartclk(void)
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{
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u32 reg, prediv, podf;
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unsigned long parent_rate;
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reg = ccm_readl(MX5_CCM_CSCMR1);
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reg &= MX5_CCM_CSCMR1_UART_CLK_SEL_MASK;
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reg >>= MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
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parent_rate = get_rate_select(reg,
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pll1_main_get_rate,
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pll2_sw_get_rate,
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pll3_sw_get_rate,
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lp_apm_get_rate);
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reg = ccm_readl(MX5_CCM_CSCDR1);
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prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
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MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
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podf = ((reg & MX5_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
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MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
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return parent_rate / (prediv * podf);
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}
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unsigned long imx_get_ahbclk(void)
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{
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u32 reg, div;
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reg = ccm_readl(MX5_CCM_CBCDR);
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div = ((reg >> 10) & 0x7) + 1;
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return pll2_sw_get_rate() / div;
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}
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unsigned long imx_get_ipgclk(void)
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{
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u32 reg, div;
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reg = ccm_readl(MX5_CCM_CBCDR);
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div = ((reg >> 8) & 0x3) + 1;
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return imx_get_ahbclk() / div;
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}
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unsigned long imx_get_gptclk(void)
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{
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return imx_get_ipgclk();
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}
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unsigned long imx_get_fecclk(void)
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{
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return imx_get_ipgclk();
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}
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unsigned long fsl_get_i2cclk(void)
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{
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return imx_get_ipgclk();
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}
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unsigned long imx_get_mmcclk(void)
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{
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u32 reg, prediv, podf, rate;
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reg = ccm_readl(MX5_CCM_CSCMR1);
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reg &= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK;
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reg >>= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
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rate = get_rate_select(reg,
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pll1_main_get_rate,
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pll2_sw_get_rate,
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pll3_sw_get_rate,
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lp_apm_get_rate);
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reg = ccm_readl(MX5_CCM_CSCDR1);
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prediv = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
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MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1;
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podf = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
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MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1;
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return rate / (prediv * podf);
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}
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unsigned long imx_get_usbclk(void)
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{
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u32 reg, prediv, podf, rate;
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reg = ccm_readl(MX5_CCM_CSCMR1);
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reg &= MX5_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
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reg >>= MX5_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
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rate = get_rate_select(reg,
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pll1_main_get_rate,
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pll2_sw_get_rate,
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pll3_sw_get_rate,
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lp_apm_get_rate);
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reg = ccm_readl(MX5_CCM_CSCDR1);
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prediv = ((reg & MX5_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
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MX5_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
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podf = ((reg & MX5_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
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MX5_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
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return rate / (prediv * podf);
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}
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unsigned long imx_get_cspiclk(void)
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{
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return 166000000; /* FIXME: bogus value */
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}
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/*
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* Set the divider of the CLKO pin. Returns
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* the new divider (which may be smaller
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* than the desired one)
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*/
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int imx_clko_set_div(int num, int div)
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{
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u32 ccosr = ccm_readl(MX5_CCM_CCOSR);
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div--;
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switch (num) {
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case 1:
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div &= 0x7;
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ccosr &= ~(0x7 << 4);
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ccosr |= div << 4;
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ccm_writel(ccosr, MX5_CCM_CCOSR);
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break;
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case 2:
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div &= 0x7;
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ccosr &= ~(0x7 << 21);
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ccosr |= div << 21;
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ccm_writel(ccosr, MX5_CCM_CCOSR);
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break;
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default:
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return -ENODEV;
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}
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return div + 1;
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}
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/*
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* Set the clock source for the CLKO pin
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*/
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void imx_clko_set_src(int num, int src)
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{
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u32 ccosr = ccm_readl(MX5_CCM_CCOSR);
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switch (num) {
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case 1:
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if (src < 0) {
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ccosr &= ~(1 << 7);
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break;
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}
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ccosr &= ~0xf;
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ccosr |= src & 0xf;
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ccosr |= 1 << 7;
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break;
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case 2:
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if (src < 0) {
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ccosr &= ~(1 << 24);
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break;
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}
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ccosr &= ~(0x1f << 16);
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ccosr |= (src & 0x1f) << 16;
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ccosr |= 1 << 24;
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break;
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default:
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return;
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}
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ccm_writel(ccosr, MX5_CCM_CCOSR);
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}
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void imx_dump_clocks(void)
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{
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printf("pll1: %ld\n", pll1_main_get_rate());
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printf("pll2: %ld\n", pll2_sw_get_rate());
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printf("pll3: %ld\n", pll3_sw_get_rate());
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printf("lp_apm: %ld\n", lp_apm_get_rate());
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printf("uart: %ld\n", imx_get_uartclk());
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printf("ipg: %ld\n", imx_get_ipgclk());
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printf("fec: %ld\n", imx_get_fecclk());
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printf("gpt: %ld\n", imx_get_gptclk());
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printf("usb: %ld\n", imx_get_usbclk());
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}
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