63 lines
2.4 KiB
C
63 lines
2.4 KiB
C
/**
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* @file
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* @brief This file contains the SMX specific register definitions
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*
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* Originally from Linux kernel:
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* http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz
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* include/asm-arm/arch-omap/omap34xx.h
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*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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* Nishanth Menon <x0nishan@ti.com>
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*
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* Copyright (C) 2007 Texas Instruments, <www.ti.com>
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* Copyright (C) 2007 Nokia Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ASM_ARCH_OMAP_SMX_H
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#define __ASM_ARCH_OMAP_SMX_H
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/* SMX-APE */
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#define PM_RT_APE_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x10000)
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#define PM_GPMC_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12400)
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#define PM_OCM_RAM_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12800)
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#define PM_OCM_ROM_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12C00)
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#define PM_IVA2_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x14000)
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#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68)
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#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50)
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#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58)
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#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60)
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#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48)
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#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50)
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#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58)
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#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48)
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#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50)
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#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58)
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#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80)
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/* IVA2 */
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#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48)
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#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50)
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#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58)
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/* SMS */
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#define SMS_SYSCONFIG (OMAP_SMS_BASE + 0x10)
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#define SMS_RG_ATT0 (OMAP_SMS_BASE + 0x48)
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#define SMS_CLASS_ARB0 (OMAP_SMS_BASE + 0xD0)
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#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
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#endif /* __ASM_ARCH_OMAP_SMX_H */
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