241 lines
6.6 KiB
ArmAsm
241 lines
6.6 KiB
ArmAsm
/*
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*
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*/
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#include <config.h>
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#include <mach/s3c24x0-iomap.h>
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.section ".text_bare_init.board_init_lowlevel","ax"
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/*
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* To be able to setup the SDRAM interface correctly, we need some
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* external information about the connected SDRAM devices.
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*
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* When we set GPH8, we can read at GPB:
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* Bit 0..1: Memory device size -> 00=16M, 01=64M, 10=32M, 11=128M
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* Bit 2: CL setting
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*
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* Some remarks: The CL setting seems useless. It always signals a CL3
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* requirement, but the SDRAM types I found on the cards are supporting
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* CL2 @ 100 MHz. But also these SDRAM types are only support 105 MHz max.
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* So, we never need CL3 because we can't run the CPU at 533 MHz (which
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* implies an 133 MHz SDRAM clock).
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* All devices are connected via 32 bit databus
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*
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* Note: I was able to check the 32 MiB and 64 MiB configuration only. I didn't
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* had access to a 16 MiB nor 128 MiB config.
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*
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*/
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sdram_init:
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/*
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* Read the configuration. After reset until any GPIO port is
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* configured yet, these pins show external settings, to detect
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* the SDRAM size.
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*/
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ldr r1, =GPBDAT
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ldr r4, [r1]
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and r4, r4, #0x3
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ldr r1, =S3C24X0_MEMCTL_BASE
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/* configure both SDRAM areas with 32 bit data bus width */
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ldr r0, =((0x2 << 24) + (0x2 << 28))
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str r0, [r1], #0x1c /* post add register offset for bank6 */
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/*
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* With the configuration we simply need to calculate an offset into
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* our table with the predefined SDRAM settings
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*/
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adr r0, SDRAMDATA
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mov r2, #6*4 /* # of bytes per table entry */
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mul r3, r4, r2
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add r0, r0, r3 /* start address of the entry */
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/*
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* store the table entry data into the registers
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*/
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1:
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ldr r3, [r0], #4
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str r3, [r1], #4
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subs r2, r2, #4
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bne 1b
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/* TODO: Check if the second bank is populated, and switch it off if not */
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mov pc, lr
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/*
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* we need 4 sets of memory settings per main CPU clock speed
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*
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* 400MHz main speed:
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* - 16 MiB in the first bank, maybe 16 MiB in the second bank (untested!)
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* - 32 MiB in the first bank, maybe 32 MiB in the second bank (CL=2)
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* - 64 MiB in the first bank, maybe 64 MiB in the second bank (CL=2)
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* - 128 MiB in the first bank, maybe 128 MiB in the second bank (untested!)
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*
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* Note: SDRAM clock runs at 100MHz
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*/
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SDRAMDATA:
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/* --------------------------- 16 MiB @ 100MHz --------------------------- */
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/*
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* - MT = 11 (= sync dram type)
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* - Trcd = 01 (= CL3)
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* - SCAN = 00 (= 8 bit collumns)
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*/
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.word ((0x3 << 15) + (0x1 << 2) + (0x0))
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.word ((0x3 << 15) + (0x1 << 2) + (0x0))
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/*
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* SDRAM refresh settings
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* - REFEN = 1 (= refresh enabled)
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* - TREFMD = 0 (= auto refresh)
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* - Trp = 00 (= 2 RAS precharge clocks)
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* - Tsrc = 11 (= 7 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
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* - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = FIXME
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*/
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.word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x3 << 18) + 468)
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/*
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* SDRAM banksize
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* - BURST_EN = 0 (= burst mode disabled)
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* - SCKE_EN = 1 (= SDRAM SCKE enabled)
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* - SCLK_EN = 1 (= clock active only during accesses)
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* - BK67MAP = 010 (= 128MiB) FIXME?????
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*/
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.word ((0 << 7) + (1 << 5) + (1 << 4) + 2)
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/*
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* SDRAM mode register
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* CL = 010 (= 2 clocks)
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*/
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.word (0x2 << 4)
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.word (0x2 << 4)
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/* ------------- one or two banks with 64 MiB @ 100MHz -------------------- */
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/*
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* - MT = 11 (= sync dram type)
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* - Trcd = 00 (= CL2)
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* - SCAN = 01 (= 9 bit collumns)
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*/
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.word ((0x3 << 15) + (0x0 << 2) + (0x1))
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.word ((0x3 << 15) + (0x0 << 2) + (0x1))
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/*
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* SDRAM refresh settings
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* - REFEN = 1 (= refresh enabled)
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* - TREFMD = 0 (= auto refresh)
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* - Trp = 00 (= 2 RAS precharge clocks)
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* - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
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* - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489
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*/
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.word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489)
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/*
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* SDRAM banksize
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* - BURST_EN = 1 (= burst mode enabled)
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* - SCKE_EN = 1 (= SDRAM SCKE enabled)
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* - SCLK_EN = 1 (= clock active only during accesses)
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* - BK67MAP = 001 (= 64 MiB)
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*/
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.word ((1 << 7) + (1 << 5) + (1 << 4) + 1)
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/*
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* SDRAM mode register
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* CL = 010 (= 2 clocks)
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*/
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.word (0x2 << 4)
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.word (0x2 << 4)
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/* ------------- one or two banks with 32 MiB @ 100MHz -------------------- */
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/*
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* - MT = 11 (= sync dram type)
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* - Trcd = 00 (= CL2)
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* - SCAN = 01 (= 9 bit collumns)
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*/
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.word ((0x3 << 15) + (0x0 << 2) + (0x1))
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.word ((0x3 << 15) + (0x0 << 2) + (0x1))
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/*
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* SDRAM refresh settings
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* - REFEN = 1 (= refresh enabled)
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* - TREFMD = 0 (= auto refresh)
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* - Trp = 00 (= 2 RAS precharge clocks)
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* - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
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* - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489
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*/
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.word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489)
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/*
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* SDRAM banksize
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* - BURST_EN = 1 (= burst mode enabled)
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* - SCKE_EN = 1 (= SDRAM SCKE enabled)
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* - SCLK_EN = 1 (= clock active only during accesses)
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* - BK67MAP = 000 (= 32 MiB)
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*/
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.word ((1 << 7) + (1 << 5) + (1 << 4) + 0)
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/*
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* SDRAM mode register
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* CL = 010 (= 2 clocks)
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*/
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.word (0x2 << 4)
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.word (0x2 << 4)
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/* ------------ one or two banks with 128 MiB @ 100MHz -------------------- */
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/*
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* - MT = 11 (= sync dram type)
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* - Trcd = 00 (= CL2)
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* - SCAN = 01 (= 9 bit collumns)
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*/
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.word ((0x3 << 15) + (0x0 << 2) + (0x1))
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.word ((0x3 << 15) + (0x0 << 2) + (0x1))
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/*
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* SDRAM refresh settings
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* - REFEN = 1 (= refresh enabled)
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* - TREFMD = 0 (= auto refresh)
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* - Trp = 00 (= 2 RAS precharge clocks)
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* - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns)
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* - Refrsh = 2^11 + 1 - 100 * 7.5 = 2049 - FIXME = 1259
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*/
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.word ((0x1 << 23) + (0x0 << 22) + (0x1 << 20) + (0x3 << 18) + 1259)
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/*
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* SDRAM banksize
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* - BURST_EN = 0 (= burst mode disabled)
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* - SCKE_EN = 1 (= SDRAM SCKE enabled)
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* - SCLK_EN = 1 (= clock active only during accesses)
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* - BK67MAP = 010 (= 128MiB)
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*/
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.word (0x32)
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/*
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* SDRAM mode register
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* CL = 010 (= 2 clocks)
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*/
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.word (0x2 << 4)
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.word (0x2 << 4)
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/* ------------------------------------------------------------------------ */
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.globl board_init_lowlevel
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board_init_lowlevel:
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mov r10, lr /* save the link register */
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bl s3c24x0_disable_wd
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/* skip everything here if we are already running from SDRAM */
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cmp pc, #S3C24X0_SDRAM_BASE
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blo 1f
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cmp pc, #S3C24X0_SDRAM_END
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bhs 1f
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mov pc, r10
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/* we are running from NOR or NAND/SRAM memory. Do further initialisation */
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1:
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bl s3c24x0_pll_init
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bl sdram_init
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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mov lr, r10 /* restore the link register */
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/* up to here we are running from the internal SRAM area */
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b s3c24x0_nand_boot /* does return directly to our caller into SDRAM */
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#else
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mov pc, r10
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#endif
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