352 lines
9.4 KiB
C
352 lines
9.4 KiB
C
/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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* 2009 Marc Kleine-Budde, Pengutronix
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* (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Derived from:
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*
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* * mx35_3stack.c - board file for uboot-v1
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <environment.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <fec.h>
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#include <fs.h>
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#include <init.h>
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#include <nand.h>
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#include <net.h>
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#include <partition.h>
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#include <asm/armlinux.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/mmu.h>
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#include <mach/gpio.h>
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#include <mach/imx-nand.h>
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#include <mach/imx-regs.h>
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#include <mach/iomux-mx35.h>
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#include <mach/iomux-v3.h>
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#include <mach/pmic.h>
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#include <mach/imx-ipu-fb.h>
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#include <mach/imx-pll.h>
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static struct fec_platform_data fec_info = {
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.xcv_type = MII100,
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.phy_addr = 0x1F,
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};
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static struct device_d fec_dev = {
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.name = "fec_imx",
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.map_base = IMX_FEC_BASE,
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.platform_data = &fec_info,
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};
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static struct memory_platform_data sdram_pdata = {
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.name = "ram0",
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.flags = DEVFS_RDWR,
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};
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static struct device_d sdram_dev = {
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.name = "mem",
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.map_base = IMX_SDRAM_CS0,
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.size = 128 * 1024 * 1024,
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.platform_data = &sdram_pdata,
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};
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struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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.flash_bbt = 1,
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};
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static struct device_d nand_dev = {
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.name = "imx_nand",
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.map_base = IMX_NFC_BASE,
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.platform_data = &nand_info,
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};
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static struct fb_videomode imxfb_mode = {
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.name = "CMO_QVGA",
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.refresh = 60,
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.xres = 320,
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.yres = 240,
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.pixclock = KHZ2PICOS(7000),
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.left_margin = 68,
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.right_margin = 20,
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.upper_margin = 15,
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.lower_margin = 4,
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.hsync_len = 30,
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.vsync_len = 3,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED,
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.flag = 0,
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};
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static void eukrea_cpuimx35_enable_display(int enable)
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{
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gpio_direction_output(4, enable);
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}
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static struct imx_ipu_fb_platform_data ipu_fb_data = {
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.mode = &imxfb_mode,
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.bpp = 16,
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.enable = eukrea_cpuimx35_enable_display,
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};
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static struct device_d imxfb_dev = {
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.name = "imx-ipu-fb",
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.map_base = 0x53fc0000,
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.size = 0x1000,
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.platform_data = &ipu_fb_data,
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};
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#ifdef CONFIG_MMU
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static int eukrea_cpuimx35_mmu_init(void)
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{
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mmu_init();
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arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
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arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
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setup_dma_coherent(0x10000000);
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#if TEXT_BASE & (0x100000 - 1)
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#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
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#else
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arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED);
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#endif
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mmu_enable();
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#ifdef CONFIG_CACHE_L2X0
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l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
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#endif
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return 0;
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}
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postcore_initcall(eukrea_cpuimx35_mmu_init);
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#endif
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static int eukrea_cpuimx35_devices_init(void)
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{
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register_device(&nand_dev);
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devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
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dev_add_bb_dev("self_raw", "self0");
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devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
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dev_add_bb_dev("env_raw", "env0");
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register_device(&fec_dev);
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register_device(&sdram_dev);
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register_device(&imxfb_dev);
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armlinux_add_dram(&sdram_dev);
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armlinux_set_bootparams((void *)0x80000100);
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armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35);
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return 0;
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}
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device_initcall(eukrea_cpuimx35_devices_init);
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static struct device_d eukrea_cpuimx35_serial_device = {
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.name = "imx_serial",
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.map_base = IMX_UART1_BASE,
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.size = 4096,
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};
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static struct pad_desc eukrea_cpuimx35_pads[] = {
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MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
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MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
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MX35_PAD_FEC_RX_DV__FEC_RX_DV,
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MX35_PAD_FEC_COL__FEC_COL,
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MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
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MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
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MX35_PAD_FEC_TX_EN__FEC_TX_EN,
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MX35_PAD_FEC_MDC__FEC_MDC,
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MX35_PAD_FEC_MDIO__FEC_MDIO,
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MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
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MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
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MX35_PAD_FEC_CRS__FEC_CRS,
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MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
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MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
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MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
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MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
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MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
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MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
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MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
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MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
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MX35_PAD_RXD1__UART1_RXD_MUX,
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MX35_PAD_TXD1__UART1_TXD_MUX,
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MX35_PAD_RTS1__UART1_RTS,
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MX35_PAD_CTS1__UART1_CTS,
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MX35_PAD_LD23__GPIO3_29,
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MX35_PAD_CONTRAST__GPIO1_1,
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MX35_PAD_D3_CLS__GPIO1_4,
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};
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static int eukrea_cpuimx35_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
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ARRAY_SIZE(eukrea_cpuimx35_pads));
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/* screen default on to prevent flicker */
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gpio_direction_output(4, 1);
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/* backlight default off */
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gpio_direction_output(1, 0);
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/* led default off */
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gpio_direction_output(32 * 2 + 29, 1);
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register_device(&eukrea_cpuimx35_serial_device);
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return 0;
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}
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console_initcall(eukrea_cpuimx35_console_init);
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static int eukrea_cpuimx35_core_init(void)
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{
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u32 reg;
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/* enable clock for I2C1 and FEC */
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reg = readl(IMX_CCM_BASE + CCM_CGR1);
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reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
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reg = writel(reg, IMX_CCM_BASE + CCM_CGR1);
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/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, IMX_AIPS1_BASE);
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writel(0x77777777, IMX_AIPS1_BASE + 0x4);
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writel(0x77777777, IMX_AIPS2_BASE);
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writel(0x77777777, IMX_AIPS2_BASE + 0x4);
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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writel(0x0, IMX_AIPS1_BASE + 0x40);
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writel(0x0, IMX_AIPS1_BASE + 0x44);
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writel(0x0, IMX_AIPS1_BASE + 0x48);
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writel(0x0, IMX_AIPS1_BASE + 0x4C);
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reg = readl(IMX_AIPS1_BASE + 0x50);
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reg &= 0x00FFFFFF;
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writel(reg, IMX_AIPS1_BASE + 0x50);
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writel(0x0, IMX_AIPS2_BASE + 0x40);
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writel(0x0, IMX_AIPS2_BASE + 0x44);
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writel(0x0, IMX_AIPS2_BASE + 0x48);
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writel(0x0, IMX_AIPS2_BASE + 0x4C);
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reg = readl(IMX_AIPS2_BASE + 0x50);
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reg &= 0x00FFFFFF;
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writel(reg, IMX_AIPS2_BASE + 0x50);
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/* MAX (Multi-Layer AHB Crossbar Switch) setup */
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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#define MAX_PARAM1 0x00302154
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
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/* SGPCR - always park on last master */
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writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */
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writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */
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writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */
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writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */
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writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */
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/* MGPCR - restore default values */
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writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */
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writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */
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writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */
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writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */
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writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */
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writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */
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/*
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* M3IF Control Register (M3IFCTL)
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* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
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* MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000
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* MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000
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* MRRP[3] = USB not on priority list (0 << 0) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
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* MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000
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* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
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* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
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* ------------
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* 0x00000040
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*/
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writel(0x40, IMX_M3IF_BASE);
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return 0;
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}
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core_initcall(eukrea_cpuimx35_core_init);
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#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
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#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
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static int do_cpufreq(struct command *cmdtp, int argc, char *argv[])
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{
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unsigned long freq;
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if (argc != 2)
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return COMMAND_ERROR_USAGE;
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freq = simple_strtoul(argv[1], NULL, 0);
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switch (freq) {
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case 399:
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writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL);
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break;
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case 532:
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writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
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break;
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default:
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return COMMAND_ERROR_USAGE;
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}
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printf("Switched CPU frequency to %dMHz\n", freq);
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return 0;
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}
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static const __maybe_unused char cmd_cpufreq_help[] =
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"Usage: cpufreq 399|532\n"
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"\n"
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"Set CPU frequency to <freq> MHz\n";
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BAREBOX_CMD_START(cpufreq)
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.cmd = do_cpufreq,
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.usage = "adjust CPU frequency",
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BAREBOX_CMD_HELP(cmd_cpufreq_help)
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BAREBOX_CMD_END
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