357 lines
9.4 KiB
C
357 lines
9.4 KiB
C
/*
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* (C) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <environment.h>
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#include <mach/imx-regs.h>
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#include <asm/armlinux.h>
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#include <mach/gpio.h>
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#include <asm/io.h>
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#include <partition.h>
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#include <asm/mach-types.h>
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#include <mach/imx-nand.h>
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#include <fec.h>
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#include <nand.h>
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#include <mach/imx-flash-header.h>
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#include <mach/iomux-mx25.h>
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#include <mach/generic.h>
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#include <linux/err.h>
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#include <i2c/i2c.h>
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#include <i2c/mc34704.h>
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extern unsigned long _stext;
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void __naked __flash_header_start go(void)
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{
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__asm__ __volatile__("b exception_vectors\n");
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}
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struct imx_dcd_entry __dcd_entry_0x400 dcd_entry[] = {
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{ .ptr_type = 4, .addr = 0xb8002050, .val = 0x0000d843, },
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{ .ptr_type = 4, .addr = 0xb8002054, .val = 0x22252521, },
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{ .ptr_type = 4, .addr = 0xb8002058, .val = 0x22220a00, },
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#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2
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{ .ptr_type = 4, .addr = 0xb8001004, .val = 0x0076e83a, },
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{ .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000304, },
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{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, },
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{ .ptr_type = 4, .addr = 0x80000f00, .val = 0x12344321, },
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{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, },
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{ .ptr_type = 1, .addr = 0x82000000, .val = 0xda, },
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{ .ptr_type = 1, .addr = 0x83000000, .val = 0xda, },
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{ .ptr_type = 1, .addr = 0x81000400, .val = 0xda, },
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{ .ptr_type = 1, .addr = 0x80000333, .val = 0xda, },
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{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, },
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{ .ptr_type = 4, .addr = 0x80000400, .val = 0x12344321, },
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{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2210000, },
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{ .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, },
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{ .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, },
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{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, },
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{ .ptr_type = 1, .addr = 0x80000233, .val = 0xda, },
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{ .ptr_type = 1, .addr = 0x81000780, .val = 0xda, },
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{ .ptr_type = 1, .addr = 0x81000400, .val = 0xda, },
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{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, },
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#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR
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{ .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, },
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{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x92100000, },
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{ .ptr_type = 1, .addr = 0x80000400, .val = 0x21, },
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{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2100000, },
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{ .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },
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{ .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },
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{ .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2100000, },
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{ .ptr_type = 1, .addr = 0x80000033, .val = 0xda, },
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{ .ptr_type = 1, .addr = 0x81000000, .val = 0xff, },
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{ .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216880, },
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{ .ptr_type = 4, .addr = 0xb8001004, .val = 0x00295729, },
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#else
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#error "Unsupported SDRAM type"
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#endif
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{ .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, },
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};
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#define APP_DEST 0x80000000
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struct imx_flash_header __flash_header_0x400 mx25_3ds_header = {
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.app_code_jump_vector = APP_DEST + 0x1000,
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.app_code_barker = APP_CODE_BARKER,
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.app_code_csf = 0,
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.dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd),
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.super_root_key = 0,
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.dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker),
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.app_dest = APP_DEST,
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.dcd_barker = DCD_BARKER,
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.dcd_block_len = sizeof (dcd_entry),
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};
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extern unsigned long __bss_start;
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unsigned long __image_len_0x400 barebox_len = 0x40000;
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static struct fec_platform_data fec_info = {
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.xcv_type = RMII,
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.phy_addr = 1,
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};
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static struct device_d fec_dev = {
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.name = "fec_imx",
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.map_base = IMX_FEC_BASE,
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.platform_data = &fec_info,
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};
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static struct memory_platform_data sdram_pdata = {
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.name = "ram0",
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.flags = DEVFS_RDWR,
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};
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static struct device_d sdram0_dev = {
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.name = "mem",
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.map_base = IMX_SDRAM_CS0,
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#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2
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.size = 64 * 1024 * 1024,
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#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR
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.size = 128 * 1024 * 1024,
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#else
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#error "Unsupported SDRAM type"
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#endif
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.platform_data = &sdram_pdata,
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};
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static struct memory_platform_data sram_pdata = {
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.name = "sram0",
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.flags = DEVFS_RDWR,
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};
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static struct device_d sram0_dev = {
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.name = "mem",
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.map_base = 0x78000000,
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.size = 128 * 1024,
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.platform_data = &sram_pdata,
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};
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struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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};
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static struct device_d nand_dev = {
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.name = "imx_nand",
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.map_base = IMX_NFC_BASE,
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.platform_data = &nand_info,
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};
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#ifdef CONFIG_USB
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static void imx25_usb_init(void)
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{
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unsigned int tmp;
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/* Host 2 */
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tmp = readl(IMX_OTG_BASE + 0x600);
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tmp &= ~(3 << 21);
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tmp |= (2 << 21) | (1 << 4) | (1 << 5);
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writel(tmp, IMX_OTG_BASE + 0x600);
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tmp = readl(IMX_OTG_BASE + 0x584);
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tmp |= 3 << 30;
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writel(tmp, IMX_OTG_BASE + 0x584);
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/* Set to Host mode */
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tmp = readl(IMX_OTG_BASE + 0x5a8);
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writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
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}
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static struct device_d usbh2_dev = {
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.name = "ehci",
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.map_base = IMX_OTG_BASE + 0x400,
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.size = 0x200,
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};
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#endif
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static struct i2c_board_info i2c_devices[] = {
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{
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I2C_BOARD_INFO("mc34704", 0x54),
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},
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};
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static struct device_d i2c_dev = {
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.name = "i2c-imx",
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.map_base = IMX_I2C1_BASE,
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};
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static int imx25_3ds_pmic_init(void)
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{
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struct mc34704 *pmic;
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pmic = mc34704_get();
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if (pmic == NULL)
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return -EIO;
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return mc34704_reg_write(pmic, 0x2, 0x9);
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}
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static int imx25_3ds_fec_init(void)
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{
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int ret;
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ret = imx25_3ds_pmic_init();
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if (ret < 0)
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return ret;
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/*
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* Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
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* Assert FEC_RESET_B, then power up the PHY by asserting
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* FEC_ENABLE, at the same time lifting FEC_RESET_B.
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*
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* FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17
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* FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12
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*/
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writel(0x8, IMX_IOMUXC_BASE + 0x0238); /* open drain */
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writel(0x0, IMX_IOMUXC_BASE + 0x028C); /* cmos, no pu/pd */
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#define FEC_ENABLE_GPIO 35
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#define FEC_RESET_B_GPIO 104
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/* make the pins output */
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gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */
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gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
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udelay(2);
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/* turn on power & lift reset */
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gpio_set_value(FEC_ENABLE_GPIO, 1);
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gpio_set_value(FEC_RESET_B_GPIO, 1);
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return 0;
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}
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late_initcall(imx25_3ds_fec_init);
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static int imx25_devices_init(void)
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{
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#ifdef CONFIG_USB
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/* USB does not work yet. Don't know why. Maybe
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* the CPLD has to be initialized.
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*/
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imx25_usb_init();
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register_device(&usbh2_dev);
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#endif
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register_device(&fec_dev);
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if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14))
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nand_info.width = 2;
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register_device(&nand_dev);
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devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
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dev_add_bb_dev("self_raw", "self0");
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devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
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dev_add_bb_dev("env_raw", "env0");
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register_device(&sdram0_dev);
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register_device(&sram0_dev);
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i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
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register_device(&i2c_dev);
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armlinux_add_dram(&sdram0_dev);
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armlinux_set_bootparams((void *)0x80000100);
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armlinux_set_architecture(MACH_TYPE_MX25_3DS);
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armlinux_set_serial(imx_uid());
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return 0;
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}
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device_initcall(imx25_devices_init);
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static struct device_d imx25_serial_device = {
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.name = "imx_serial",
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.map_base = IMX_UART1_BASE,
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.size = 16 * 1024,
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};
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static struct pad_desc imx25_pads[] = {
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MX25_PAD_FEC_MDC__MDC,
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MX25_PAD_FEC_MDIO__MDIO,
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MX25_PAD_FEC_RDATA0__RDATA0,
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MX25_PAD_FEC_RDATA1__RDATA1,
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MX25_PAD_FEC_RX_DV__RX_DV,
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MX25_PAD_FEC_TDATA0__TDATA0,
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MX25_PAD_FEC_TDATA1__TDATA1,
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MX25_PAD_FEC_TX_CLK__TX_CLK,
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MX25_PAD_FEC_TX_EN__TX_EN,
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MX25_PAD_POWER_FAIL__POWER_FAIL_INT,
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MX25_PAD_A17__GPIO3,
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MX25_PAD_D12__GPIO8,
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/* UART1 */
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MX25_PAD_UART1_RXD__RXD_MUX,
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MX25_PAD_UART1_TXD__TXD_MUX,
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MX25_PAD_UART1_RTS__RTS,
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MX25_PAD_UART1_CTS__CTS,
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/* USBH2 */
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MX25_PAD_D9__USBH2_PWR,
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MX25_PAD_D8__USBH2_OC,
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MX25_PAD_LD0__USBH2_CLK,
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MX25_PAD_LD1__USBH2_DIR,
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MX25_PAD_LD2__USBH2_STP,
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MX25_PAD_LD3__USBH2_NXT,
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MX25_PAD_LD4__USBH2_DATA0,
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MX25_PAD_LD5__USBH2_DATA1,
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MX25_PAD_LD6__USBH2_DATA2,
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MX25_PAD_LD7__USBH2_DATA3,
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MX25_PAD_HSYNC__USBH2_DATA4,
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MX25_PAD_VSYNC__USBH2_DATA5,
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MX25_PAD_LSCLK__USBH2_DATA6,
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MX25_PAD_OE_ACD__USBH2_DATA7,
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/* i2c */
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MX25_PAD_I2C1_CLK__SCL,
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MX25_PAD_I2C1_DAT__SDA,
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};
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static int imx25_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(imx25_pads, ARRAY_SIZE(imx25_pads));
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writel(0x03010101, 0x53f80024);
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register_device(&imx25_serial_device);
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return 0;
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}
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console_initcall(imx25_console_init);
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#ifdef CONFIG_NAND_IMX_BOOT
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void __bare_init nand_boot(void)
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{
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imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
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}
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#endif
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static int imx25_core_setup(void)
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{
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writel(0x01010103, IMX_CCM_BASE + CCM_PCDR2);
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return 0;
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}
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core_initcall(imx25_core_setup);
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