125 lines
3.9 KiB
C
125 lines
3.9 KiB
C
/**
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* @file
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* @brief Contains the PRM and CM definitions
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*
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* FileName: include/asm-arm/arch-omap/omap3-clock.h
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*
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* Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz
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*
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*/
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/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _OMAP343X_CLOCKS_H_
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#define _OMAP343X_CLOCKS_H_
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/** CM Clock Regs Wrapper */
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#define CM_REG(REGNAME) (OMAP_CM_BASE + CM_##REGNAME)
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#define CM_FCLKEN_IVA2 0X0000
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#define CM_CLKEN_PLL_IVA2 0X0004
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#define CM_IDLEST_PLL_IVA2 0X0024
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#define CM_CLKSEL1_PLL_IVA2 0X0040
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#define CM_CLKSEL2_PLL_IVA2 0X0044
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#define CM_CLKEN_PLL_MPU 0X0904
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#define CM_IDLEST_PLL_MPU 0X0924
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#define CM_CLKSEL1_PLL_MPU 0X0940
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#define CM_CLKSEL2_PLL_MPU 0X0944
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#define CM_FCLKEN1_CORE 0X0A00
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#define CM_ICLKEN1_CORE 0X0A10
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#define CM_ICLKEN2_CORE 0X0A14
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#define CM_CLKSEL_CORE 0X0A40
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#define CM_FCLKEN_GFX 0X0B00
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#define CM_ICLKEN_GFX 0X0B10
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#define CM_CLKSEL_GFX 0X0B40
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#define CM_FCLKEN_WKUP 0X0C00
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#define CM_ICLKEN_WKUP 0X0C10
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#define CM_CLKSEL_WKUP 0X0C40
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#define CM_IDLEST_WKUP 0X0C20
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#define CM_CLKEN_PLL 0X0D00
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#define CM_IDLEST_CKGEN 0X0D20
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#define CM_CLKSEL1_PLL 0X0D40
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#define CM_CLKSEL2_PLL 0X0D44
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#define CM_CLKSEL3_PLL 0X0D48
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#define CM_FCLKEN_DSS 0X0E00
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#define CM_ICLKEN_DSS 0X0E10
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#define CM_CLKSEL_DSS 0X0E40
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#define CM_FCLKEN_CAM 0X0F00
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#define CM_ICLKEN_CAM 0X0F10
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#define CM_CLKSEL_CAM 0X0f40
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#define CM_FCLKEN_PER 0X1000
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#define CM_ICLKEN_PER 0X1010
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#define CM_CLKSEL_PER 0X1040
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#define CM_CLKSEL1_EMU 0X1140
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/** PRM Clock Regs */
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#define PRM_REG(REGNAME) (OMAP_PRM_BASE + PRM_##REGNAME)
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#define PRM_CLKSEL 0x0D40
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#define PRM_RSTCTRL 0x1250
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#define PRM_CLKSRC_CTRL 0x1270
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/*************** Clock Values */
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#define PLL_STOP 1 /* PER & IVA */
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#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */
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#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */
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#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */
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/* The following configurations are OPP and SysClk value independant
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* and hence are defined here.
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*/
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/* CORE DPLL */
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#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */
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#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */
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#define CORE_FUSB_DIV 2 /* 41.5MHz: */
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#define CORE_L4_DIV 2 /* 83MHz : L4 */
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#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
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#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */
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#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
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/* PER DPLL */
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#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */
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#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */
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#define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */
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#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */
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#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50))
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#define MAX_SIL_INDEX 1
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#ifndef __ASSEMBLY__
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void prcm_init(void);
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/* Used to index into DPLL parameter tables -See TRM for further details */
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struct dpll_param {
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unsigned int m;
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unsigned int n;
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unsigned int fsel;
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unsigned int m2;
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};
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/* External functions see omap3_clock_core.S */
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extern struct dpll_param *get_mpu_dpll_param(void);
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extern struct dpll_param *get_iva_dpll_param(void);
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extern struct dpll_param *get_core_dpll_param(void);
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extern struct dpll_param *get_per_dpll_param(void);
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#endif /* __ASSEMBLY__ */
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#endif /* endif _OMAP343X_CLOCKS_H_ */
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