146 lines
3.5 KiB
C
146 lines
3.5 KiB
C
/*
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* Copyright
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* (C) 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <ns16550.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <asm/memory.h>
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#include <mach/dove-regs.h>
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#define CONSOLE_UART_BASE DOVE_UARTn_BASE(CONFIG_MVEBU_CONSOLE_UART)
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static struct clk *tclk;
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static inline void dove_remap_mc_regs(void)
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{
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void __iomem *mcboot = IOMEM(DOVE_BOOTUP_MC_REGS);
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uint32_t val;
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/* remap ahb slave base */
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val = readl(DOVE_CPU_CTRL) & 0xffff0000;
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val |= (DOVE_REMAP_MC_REGS & 0xffff0000) >> 16;
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writel(val, DOVE_CPU_CTRL);
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/* remap axi bridge address */
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val = readl(DOVE_AXI_CTRL) & 0x007fffff;
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val |= DOVE_REMAP_MC_REGS & 0xff800000;
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writel(val, DOVE_AXI_CTRL);
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/* remap memory controller base address */
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val = readl(mcboot + SDRAM_REGS_BASE_DECODE) & 0x0000ffff;
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val |= DOVE_REMAP_MC_REGS & 0xffff0000;
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writel(val, mcboot + SDRAM_REGS_BASE_DECODE);
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}
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static inline void dove_memory_find(unsigned long *phys_base,
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unsigned long *phys_size)
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{
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int n;
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*phys_base = ~0;
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*phys_size = 0;
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for (n = 0; n < 2; n++) {
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uint32_t map = readl(DOVE_SDRAM_BASE + SDRAM_MAPn(n));
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uint32_t base, size;
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/* skip disabled areas */
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if ((map & SDRAM_MAP_VALID) != SDRAM_MAP_VALID)
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continue;
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base = map & SDRAM_START_MASK;
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if (base < *phys_base)
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*phys_base = base;
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/* real size is encoded as ld(2^(16+length)) */
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size = (map & SDRAM_LENGTH_MASK) >> SDRAM_LENGTH_SHIFT;
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*phys_size += 1 << (16 + size);
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}
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}
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static struct NS16550_plat uart_plat = {
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.shift = 2,
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};
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static int dove_add_uart(void)
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{
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uart_plat.clock = clk_get_rate(tclk);
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if (!add_ns16550_device(DEVICE_ID_DYNAMIC,
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(unsigned int)CONSOLE_UART_BASE, 32,
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IORESOURCE_MEM_32BIT, &uart_plat))
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return -ENODEV;
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return 0;
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}
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/*
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* Dove TCLK sample-at-reset configuation
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*
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* SAR0[24:23] : TCLK frequency
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* 0 = 166 MHz
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* 1 = 125 MHz
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* others reserved.
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*/
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static int dove_init_clocks(void)
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{
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uint32_t strap, sar = readl(DOVE_SAR_BASE + SAR0);
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unsigned int rate;
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strap = (sar & TCLK_FREQ_MASK) >> TCLK_FREQ_SHIFT;
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switch (strap) {
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case 0:
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rate = 166666667;
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break;
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case 1:
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rate = 125000000;
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break;
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default:
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panic("Unknown TCLK strapping %d\n", strap);
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}
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tclk = clk_fixed("tclk", rate);
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return clk_register_clkdev(tclk, NULL, "orion-timer");
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}
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static int dove_init_soc(void)
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{
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unsigned long phys_base, phys_size;
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dove_remap_mc_regs();
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dove_init_clocks();
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add_generic_device("orion-timer", DEVICE_ID_SINGLE, NULL,
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(unsigned int)DOVE_TIMER_BASE, 0x30,
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IORESOURCE_MEM, NULL);
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dove_memory_find(&phys_base, &phys_size);
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arm_add_mem_device("ram0", phys_base, phys_size);
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dove_add_uart();
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return 0;
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}
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postcore_initcall(dove_init_soc);
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void __noreturn reset_cpu(unsigned long addr)
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{
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/* enable and assert RSTOUTn */
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writel(SOFT_RESET_OUT_EN, DOVE_BRIDGE_BASE + BRIDGE_RSTOUT_MASK);
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writel(SOFT_RESET_EN, DOVE_BRIDGE_BASE + BRIDGE_SYS_SOFT_RESET);
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while (1)
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;
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}
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EXPORT_SYMBOL(reset_cpu);
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