499 lines
14 KiB
C
499 lines
14 KiB
C
/*
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* On-Chip devices setup code for the AT91SAM9x5 family
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*
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* Copyright (C) 2010 Atmel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <sizes.h>
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#include <gpio.h>
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#include <asm/armlinux.h>
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#include <asm/hardware.h>
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#include <mach/board.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91sam9x5_matrix.h>
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#include <mach/at91sam9_ddrsdr.h>
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#include <mach/iomux.h>
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#include <mach/io.h>
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#include <mach/cpu.h>
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#include <i2c/i2c-gpio.h>
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#include "generic.h"
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void at91_add_device_sdram(u32 size)
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{
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if (!size)
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size = at91sama5_get_ddram_size();
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arm_add_mem_device("ram0", SAMA5_DDRCS, size);
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add_mem_device("sram0", SAMA5D3_SRAM_BASE,
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SAMA5D3_SRAM_SIZE, IORESOURCE_MEM_WRITEABLE);
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}
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/* --------------------------------------------------------------------
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* NAND / SmartMedia
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* -------------------------------------------------------------------- */
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#if defined(CONFIG_NAND_ATMEL)
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static struct resource nand_resources[] = {
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[0] = {
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.start = SAMA5_CHIPSELECT_3,
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.end = SAMA5_CHIPSELECT_3 + SZ_256M - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = SAMA5D3_BASE_PMECC,
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.end = SAMA5D3_BASE_PMECC + 0x490 - 1,
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.flags = IORESOURCE_MEM,
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},
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[2] = {
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.start = SAMA5D3_BASE_PMERRLOC,
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.end = SAMA5D3_BASE_PMERRLOC + 0x100 - 1,
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.flags = IORESOURCE_MEM,
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},
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[3] = {
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.start = SAMA5D3_ROM_BASE,
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.end = SAMA5D3_ROM_BASE + SAMA5D3_ROM_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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void __init at91_add_device_nand(struct atmel_nand_data *data)
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{
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if (!data)
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return;
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switch (data->pmecc_sector_size) {
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case 512:
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data->pmecc_lookup_table_offset = 0x10000;
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break;
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case 1024:
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data->pmecc_lookup_table_offset = 0x18000;
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break;
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default:
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pr_err("%s: invalid pmecc_sector_size (%d)\n", __func__,
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data->pmecc_sector_size);
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return;
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}
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at91_set_A_periph(AT91_PIN_PE21, 1); /* ALE */
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at91_set_A_periph(AT91_PIN_PE22, 1); /* CLE */
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/* enable pin */
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if (gpio_is_valid(data->enable_pin))
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at91_set_gpio_output(data->enable_pin, 1);
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/* ready/busy pin */
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if (gpio_is_valid(data->rdy_pin))
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at91_set_gpio_input(data->rdy_pin, 1);
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/* card detect pin */
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if (gpio_is_valid(data->det_pin))
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at91_set_gpio_input(data->det_pin, 1);
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add_generic_device_res("atmel_nand", 0, nand_resources,
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ARRAY_SIZE(nand_resources), data);
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}
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#else
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void __init at91_add_device_nand(struct atmel_nand_data *data) {}
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#endif
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#if defined(CONFIG_DRIVER_NET_MACB)
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void at91_add_device_eth(int id, struct macb_platform_data *data)
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{
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if (!data)
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return;
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switch (id) {
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case 0:
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if (cpu_is_sama5d31()) {
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pr_warn("AT91: no gmac on sama5d31\n");
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return;
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}
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at91_set_A_periph(AT91_PIN_PB16, 0); /* GMDC */
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at91_set_A_periph(AT91_PIN_PB17, 0); /* GMDIO */
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at91_set_A_periph(AT91_PIN_PB9, 0); /* GTXEN */
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at91_set_A_periph(AT91_PIN_PB11, 0); /* GRXCK */
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at91_set_A_periph(AT91_PIN_PB13, 0); /* GRXER */
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switch (data->phy_interface) {
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case PHY_INTERFACE_MODE_GMII:
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at91_set_B_periph(AT91_PIN_PB19, 0); /* GTX4 */
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at91_set_B_periph(AT91_PIN_PB20, 0); /* GTX5 */
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at91_set_B_periph(AT91_PIN_PB21, 0); /* GTX6 */
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at91_set_B_periph(AT91_PIN_PB22, 0); /* GTX7 */
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at91_set_B_periph(AT91_PIN_PB23, 0); /* GRX4 */
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at91_set_B_periph(AT91_PIN_PB24, 0); /* GRX5 */
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at91_set_B_periph(AT91_PIN_PB25, 0); /* GRX6 */
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at91_set_B_periph(AT91_PIN_PB26, 0); /* GRX7 */
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case PHY_INTERFACE_MODE_MII:
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case PHY_INTERFACE_MODE_RGMII:
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at91_set_A_periph(AT91_PIN_PB0, 0); /* GTX0 */
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at91_set_A_periph(AT91_PIN_PB1, 0); /* GTX1 */
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at91_set_A_periph(AT91_PIN_PB2, 0); /* GTX2 */
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at91_set_A_periph(AT91_PIN_PB3, 0); /* GTX3 */
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at91_set_A_periph(AT91_PIN_PB4, 0); /* GRX0 */
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at91_set_A_periph(AT91_PIN_PB5, 0); /* GRX1 */
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at91_set_A_periph(AT91_PIN_PB6, 0); /* GRX2 */
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at91_set_A_periph(AT91_PIN_PB7, 0); /* GRX3 */
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break;
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default:
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return;
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}
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switch (data->phy_interface) {
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case PHY_INTERFACE_MODE_MII:
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at91_set_A_periph(AT91_PIN_PB8, 0); /* GTXCK */
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at91_set_A_periph(AT91_PIN_PB10, 0); /* GTXER */
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at91_set_A_periph(AT91_PIN_PB12, 0); /* GRXDV */
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at91_set_A_periph(AT91_PIN_PB14, 0); /* GCRS */
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at91_set_A_periph(AT91_PIN_PB15, 0); /* GCOL */
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break;
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case PHY_INTERFACE_MODE_RGMII:
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at91_set_A_periph(AT91_PIN_PB8, 0); /* GTXCK */
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at91_set_A_periph(AT91_PIN_PB18, 0); /* G125CK */
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break;
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case PHY_INTERFACE_MODE_GMII:
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at91_set_A_periph(AT91_PIN_PB10, 0); /* GTXER */
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at91_set_A_periph(AT91_PIN_PB12, 0); /* GRXDV */
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at91_set_A_periph(AT91_PIN_PB14, 0); /* GCRS */
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at91_set_A_periph(AT91_PIN_PB15, 0); /* GCOL */
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at91_set_A_periph(AT91_PIN_PB27, 0); /* G125CK0 */
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break;
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default:
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return;
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}
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add_generic_device("macb", id, NULL, SAMA5D3_BASE_GMAC, SZ_16K,
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IORESOURCE_MEM, data);
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break;
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case 1:
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if (cpu_is_sama5d33() || cpu_is_sama5d34()) {
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pr_warn("AT91: no macb on sama5d33/d34\n");
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return;
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}
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if (data->phy_interface != PHY_INTERFACE_MODE_RMII) {
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pr_warn("AT91: Only RMII available on interfacr macb%d.\n", id);
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return;
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}
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at91_set_A_periph(AT91_PIN_PC7, 0); /* ETXCK_EREFCK */
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at91_set_A_periph(AT91_PIN_PC5, 0); /* ERXDV */
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at91_set_A_periph(AT91_PIN_PC2, 0); /* ERX0 */
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at91_set_A_periph(AT91_PIN_PC3, 0); /* ERX1 */
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at91_set_A_periph(AT91_PIN_PC6, 0); /* ERXER */
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at91_set_A_periph(AT91_PIN_PC4, 0); /* ETXEN */
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at91_set_A_periph(AT91_PIN_PC0, 0); /* ETX0 */
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at91_set_A_periph(AT91_PIN_PC1, 0); /* ETX1 */
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at91_set_A_periph(AT91_PIN_PC9, 0); /* EMDIO */
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at91_set_A_periph(AT91_PIN_PC8, 0); /* EMDC */
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add_generic_device("macb", id, NULL, SAMA5D3_BASE_EMAC, SZ_16K,
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IORESOURCE_MEM, data);
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break;
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default:
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return;
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}
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}
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#else
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void at91_add_device_eth(int id, struct macb_platform_data *data) {}
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#endif
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#if defined(CONFIG_MCI_ATMEL)
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/* Consider only one slot : slot 0 */
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void __init at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
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{
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resource_size_t start = ~0;
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if (!data)
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return;
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/* Must have at least one usable slot */
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if (!data->bus_width)
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return;
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/* input/irq */
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if (gpio_is_valid(data->detect_pin)) {
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at91_set_gpio_input(data->detect_pin, 1);
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at91_set_deglitch(data->detect_pin, 1);
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}
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if (gpio_is_valid(data->wp_pin))
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at91_set_gpio_input(data->wp_pin, 1);
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switch (mmc_id) {
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case 0: /* MCI0 */
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start = SAMA5D3_BASE_HSMCI0;
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/* CLK */
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at91_set_A_periph(AT91_PIN_PD9, 0);
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/* CMD */
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at91_set_A_periph(AT91_PIN_PD0, 1);
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/* DAT0, maybe DAT1..DAT3 */
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at91_set_A_periph(AT91_PIN_PD1, 1);
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switch (data->bus_width) {
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case 8:
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at91_set_A_periph(AT91_PIN_PD5, 1);
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at91_set_A_periph(AT91_PIN_PD6, 1);
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at91_set_A_periph(AT91_PIN_PD7, 1);
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at91_set_A_periph(AT91_PIN_PD8, 1);
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case 4:
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at91_set_A_periph(AT91_PIN_PD2, 1);
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at91_set_A_periph(AT91_PIN_PD3, 1);
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at91_set_A_periph(AT91_PIN_PD4, 1);
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};
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break;
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case 1: /* MCI1 */
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start = SAMA5D3_BASE_HSMCI1;
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/* CLK */
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at91_set_A_periph(AT91_PIN_PB24, 0);
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/* CMD */
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at91_set_A_periph(AT91_PIN_PB19, 1);
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/* DAT0, maybe DAT1..DAT3 */
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at91_set_A_periph(AT91_PIN_PB20, 1);
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if (data->bus_width == 4) {
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at91_set_A_periph(AT91_PIN_PB21, 1);
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at91_set_A_periph(AT91_PIN_PB22, 1);
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at91_set_A_periph(AT91_PIN_PB23, 1);
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}
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break;
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case 2: /* MCI2 */
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start = SAMA5D3_BASE_HSMCI2;
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/* CLK */
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at91_set_A_periph(AT91_PIN_PC15, 0);
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/* CMD */
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at91_set_A_periph(AT91_PIN_PC10, 1);
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/* DAT0, maybe DAT1..DAT3 */
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at91_set_A_periph(AT91_PIN_PC11, 1);
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if (data->bus_width == 4) {
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at91_set_A_periph(AT91_PIN_PC12, 1);
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at91_set_A_periph(AT91_PIN_PC13, 1);
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at91_set_A_periph(AT91_PIN_PC14, 1);
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}
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}
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add_generic_device("atmel_mci", mmc_id, NULL, start, SZ_16K,
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IORESOURCE_MEM, data);
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}
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#else
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void __init at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {}
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#endif
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#if defined(CONFIG_I2C_GPIO)
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static struct i2c_gpio_platform_data pdata_i2c [] = {
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{
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.sda_pin = AT91_PIN_PA30,
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.sda_is_open_drain = 1,
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.scl_pin = AT91_PIN_PA31,
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.scl_is_open_drain = 1,
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.udelay = 5, /* ~100 kHz */
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}, {
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.sda_pin = AT91_PIN_PC26,
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.sda_is_open_drain = 1,
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.scl_pin = AT91_PIN_PC27,
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.scl_is_open_drain = 1,
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.udelay = 5, /* ~100 kHz */
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}, {
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.sda_pin = AT91_PIN_PA18,
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.sda_is_open_drain = 1,
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.scl_pin = AT91_PIN_PA19,
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.scl_is_open_drain = 1,
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.udelay = 5, /* ~100 kHz */
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}
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};
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void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
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{
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struct i2c_gpio_platform_data *pdata;
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if (i2c_id > ARRAY_SIZE(pdata_i2c))
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return;
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i2c_register_board_info(i2c_id, devices, nr_devices);
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pdata = &pdata_i2c[i2c_id];
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at91_set_GPIO_periph(pdata->sda_pin, 1); /* TWD (SDA) */
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at91_set_multi_drive(pdata->sda_pin, 1);
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at91_set_GPIO_periph(pdata->scl_pin, 1); /* TWCK (SCL) */
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at91_set_multi_drive(pdata->scl_pin, 1);
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add_generic_device_res("i2c-gpio", i2c_id, NULL, 0, pdata);
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}
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#else
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void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
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#endif
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/* --------------------------------------------------------------------
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* SPI
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* -------------------------------------------------------------------- */
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#if defined(CONFIG_DRIVER_SPI_ATMEL)
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static unsigned spi0_standard_cs[4] = { AT91_PIN_PD13, AT91_PIN_PD14, AT91_PIN_PD15, AT91_PIN_PD16 };
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static unsigned spi1_standard_cs[4] = { AT91_PIN_PC25, AT91_PIN_PC26, AT91_PIN_PC27, AT91_PIN_PC28 };
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static struct at91_spi_platform_data spi_pdata[] = {
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[0] = {
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.chipselect = spi0_standard_cs,
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.num_chipselect = ARRAY_SIZE(spi0_standard_cs),
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},
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[1] = {
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.chipselect = spi1_standard_cs,
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.num_chipselect = ARRAY_SIZE(spi1_standard_cs),
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},
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};
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void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata)
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{
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int i;
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int cs_pin;
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resource_size_t start = ~0;
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BUG_ON(spi_id > 1);
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if (!pdata)
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pdata = &spi_pdata[spi_id];
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for (i = 0; i < pdata->num_chipselect; i++) {
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cs_pin = pdata->chipselect[i];
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/* enable chip-select pin */
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if (gpio_is_valid(cs_pin))
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at91_set_gpio_output(cs_pin, 1);
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}
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/* Configure SPI bus(es) */
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switch (spi_id) {
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case 0:
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start = SAMA5D3_BASE_SPI0;
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at91_set_A_periph(AT91_PIN_PD10, 0); /* SPI0_MISO */
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at91_set_A_periph(AT91_PIN_PD11, 0); /* SPI0_MOSI */
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at91_set_A_periph(AT91_PIN_PD12, 0); /* SPI0_SPCK */
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break;
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case 1:
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start = SAMA5D3_BASE_SPI1;
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at91_set_B_periph(AT91_PIN_PC22, 0); /* SPI1_MISO */
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at91_set_B_periph(AT91_PIN_PC23, 0); /* SPI1_MOSI */
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at91_set_B_periph(AT91_PIN_PC24, 0); /* SPI1_SPCK */
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break;
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}
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add_generic_device("atmel_spi", spi_id, NULL, start, SZ_16K,
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IORESOURCE_MEM, pdata);
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}
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#else
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void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {}
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#endif
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/* --------------------------------------------------------------------
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* LCD Controller
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* -------------------------------------------------------------------- */
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#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD)
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void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data)
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{
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BUG_ON(!data);
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if (cpu_is_sama5d35()) {
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pr_warn("AT91: no lcd on sama5d35\n");
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return;
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}
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at91_set_A_periph(AT91_PIN_PA24, 0); /* LCDPWM */
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at91_set_A_periph(AT91_PIN_PA25, 0); /* LCDDISP */
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at91_set_A_periph(AT91_PIN_PA26, 0); /* LCDVSYNC */
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at91_set_A_periph(AT91_PIN_PA27, 0); /* LCDHSYNC */
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at91_set_A_periph(AT91_PIN_PA28, 0); /* LCDDOTCK */
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at91_set_A_periph(AT91_PIN_PA29, 0); /* LCDDEN */
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at91_set_A_periph(AT91_PIN_PA0, 0); /* LCDD0 */
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at91_set_A_periph(AT91_PIN_PA1, 0); /* LCDD1 */
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at91_set_A_periph(AT91_PIN_PA2, 0); /* LCDD2 */
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at91_set_A_periph(AT91_PIN_PA3, 0); /* LCDD3 */
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at91_set_A_periph(AT91_PIN_PA4, 0); /* LCDD4 */
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at91_set_A_periph(AT91_PIN_PA5, 0); /* LCDD5 */
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at91_set_A_periph(AT91_PIN_PA6, 0); /* LCDD6 */
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at91_set_A_periph(AT91_PIN_PA7, 0); /* LCDD7 */
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at91_set_A_periph(AT91_PIN_PA8, 0); /* LCDD8 */
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at91_set_A_periph(AT91_PIN_PA9, 0); /* LCDD9 */
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at91_set_A_periph(AT91_PIN_PA10, 0); /* LCDD10 */
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at91_set_A_periph(AT91_PIN_PA11, 0); /* LCDD11 */
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at91_set_A_periph(AT91_PIN_PA12, 0); /* LCDD12 */
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at91_set_A_periph(AT91_PIN_PA13, 0); /* LCDD13 */
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at91_set_A_periph(AT91_PIN_PA14, 0); /* LCDD14 */
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at91_set_A_periph(AT91_PIN_PA15, 0); /* LCDD15 */
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at91_set_C_periph(AT91_PIN_PC14, 0); /* LCDD16 */
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at91_set_C_periph(AT91_PIN_PC13, 0); /* LCDD17 */
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|
at91_set_C_periph(AT91_PIN_PC12, 0); /* LCDD18 */
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at91_set_C_periph(AT91_PIN_PC11, 0); /* LCDD19 */
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|
at91_set_C_periph(AT91_PIN_PC10, 0); /* LCDD20 */
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|
at91_set_C_periph(AT91_PIN_PC15, 0); /* LCDD21 */
|
|
at91_set_C_periph(AT91_PIN_PE27, 0); /* LCDD22 */
|
|
at91_set_C_periph(AT91_PIN_PE28, 0); /* LCDD23 */
|
|
|
|
add_generic_device("atmel_hlcdfb", DEVICE_ID_SINGLE, NULL, SAMA5D3_BASE_LCDC, SZ_4K,
|
|
IORESOURCE_MEM, data);
|
|
}
|
|
#else
|
|
void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {}
|
|
#endif
|
|
|
|
/* --------------------------------------------------------------------
|
|
* UART
|
|
* -------------------------------------------------------------------- */
|
|
|
|
#if defined(CONFIG_DRIVER_SERIAL_ATMEL)
|
|
resource_size_t __init at91_configure_dbgu(void)
|
|
{
|
|
at91_set_A_periph(AT91_PIN_PB30, 0); /* DRXD */
|
|
at91_set_A_periph(AT91_PIN_PB31, 1); /* DTXD */
|
|
|
|
return AT91_BASE_DBGU1;
|
|
}
|
|
|
|
resource_size_t __init at91_configure_usart0(unsigned pins)
|
|
{
|
|
at91_set_A_periph(AT91_PIN_PD18, 1); /* TXD0 */
|
|
at91_set_A_periph(AT91_PIN_PD17, 0); /* RXD0 */
|
|
|
|
if (pins & ATMEL_UART_RTS)
|
|
at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS0 */
|
|
if (pins & ATMEL_UART_CTS)
|
|
at91_set_A_periph(AT91_PIN_PD15, 0); /* CTS0 */
|
|
|
|
return SAMA5D3_BASE_USART0;
|
|
}
|
|
|
|
resource_size_t __init at91_configure_usart1(unsigned pins)
|
|
{
|
|
at91_set_A_periph(AT91_PIN_PB29, 1); /* TXD1 */
|
|
at91_set_A_periph(AT91_PIN_PB28, 0); /* RXD1 */
|
|
|
|
if (pins & ATMEL_UART_RTS)
|
|
at91_set_A_periph(AT91_PIN_PB27, 0); /* RTS1 */
|
|
if (pins & ATMEL_UART_CTS)
|
|
at91_set_A_periph(AT91_PIN_PB26, 0); /* CTS1 */
|
|
|
|
return SAMA5D3_BASE_USART1;
|
|
}
|
|
#endif
|