191 lines
4.6 KiB
C
191 lines
4.6 KiB
C
/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "pcm038: " fmt
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#include <bootsource.h>
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#include <common.h>
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#include <gpio.h>
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#include <init.h>
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#include <io.h>
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#include <notifier.h>
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#include <sizes.h>
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#include <envfs.h>
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#include <mach/devices-imx27.h>
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#include <mach/imx-pll.h>
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#include <mach/imx27-regs.h>
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#include <mach/imxfb.h>
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#include <mach/iomux-mx27.h>
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#include <mfd/mc13xxx.h>
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#include <mach/bbu.h>
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#include "pll.h"
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#define PCM038_GPIO_OTG_STP (GPIO_PORTE + 1)
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static struct imx_fb_videomode imxfb_mode = {
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.mode = {
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.name = "Sharp-LQ035Q7",
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.refresh = 60,
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.xres = 240,
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.yres = 320,
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.pixclock = 188679, /* in ps (5.3MHz) */
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.hsync_len = 7,
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.left_margin = 5,
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.right_margin = 16,
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.vsync_len = 1,
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.upper_margin = 7,
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.lower_margin = 9,
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},
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/*
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* - HSYNC active high
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* - VSYNC active high
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* - clk notenabled while idle
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* - clock not inverted
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* - data not inverted
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* - data enable low active
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* - enable sharp mode
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*/
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.pcr = 0xf00080c0,
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.bpp = 16,
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};
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static struct imx_fb_platform_data pcm038_fb_data = {
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.mode = &imxfb_mode,
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.num_modes = 1,
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.pwmr = 0x00a903ff,
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.lscr1 = 0x00120300,
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.dmacr = 0x00020010,
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};
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static const unsigned int pcm038_pins[] = {
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/* Display */
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PA5_PF_LSCLK,
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PA6_PF_LD0,
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PA7_PF_LD1,
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PA8_PF_LD2,
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PA9_PF_LD3,
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PA10_PF_LD4,
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PA11_PF_LD5,
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PA12_PF_LD6,
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PA13_PF_LD7,
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PA14_PF_LD8,
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PA15_PF_LD9,
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PA16_PF_LD10,
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PA17_PF_LD11,
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PA18_PF_LD12,
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PA19_PF_LD13,
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PA20_PF_LD14,
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PA21_PF_LD15,
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PA22_PF_LD16,
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PA23_PF_LD17,
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PA24_PF_REV,
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PA25_PF_CLS,
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PA26_PF_PS,
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PA27_PF_SPL_SPR,
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PA28_PF_HSYNC,
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PA29_PF_VSYNC,
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PA30_PF_CONTRAST,
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PA31_PF_OE_ACD,
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/* USB */
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PE1_PF_USBOTG_STP,
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};
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static int pcm038_init(void)
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{
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struct mc13xxx *mc13xxx = mc13xxx_get();
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char *envdev;
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uint32_t i, bbu_nand_flags = 0, bbu_nor_flags = 0;
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if (!of_machine_is_compatible("phytec,imx27-pcm038"))
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return 0;
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/* Apply delay for STP line to stop ULPI */
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imx_gpio_mode(PCM038_GPIO_OTG_STP | GPIO_GPIO);
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gpio_direction_output(PCM038_GPIO_OTG_STP, 1);
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mdelay(1);
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for (i = 0; i < ARRAY_SIZE(pcm038_pins); i++)
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imx_gpio_mode(pcm038_pins[i]);
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imx27_add_fb(&pcm038_fb_data);
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switch (bootsource_get()) {
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case BOOTSOURCE_NAND:
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of_device_enable_path("/chosen/environment-nand");
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bbu_nand_flags |= BBU_HANDLER_FLAG_DEFAULT;
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envdev = "NAND";
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break;
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default:
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of_device_enable_path("/chosen/environment-nor");
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bbu_nor_flags |= BBU_HANDLER_FLAG_DEFAULT;
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envdev = "NOR";
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break;
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}
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pr_notice("Using environment in %s Flash\n", envdev);
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if (!mc13xxx) {
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pr_err("Failed to initialize PMIC. Will continue with low CPU speed\n");
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return 0;
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}
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mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0),
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MC13783_SWX_VOLTAGE(MC13783_SWX_VOLTAGE_1_450) |
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MC13783_SWX_VOLTAGE_DVS(MC13783_SWX_VOLTAGE_1_450) |
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MC13783_SWX_VOLTAGE_STANDBY(MC13783_SWX_VOLTAGE_1_450));
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mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(4),
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MC13783_SW1A_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) |
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MC13783_SW1A_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) |
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MC13783_SW1A_SOFTSTART |
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MC13783_SW1B_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) |
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MC13783_SW1B_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) |
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MC13783_SW1B_SOFTSTART |
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MC13783_SW_PLL_FACTOR(32));
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if (IS_ENABLED(CONFIG_MCI_IMX)) {
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/* VMMC1 = 3.00 V */
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mc13xxx_set_bits(mc13xxx, MC13783_REG_REG_SETTING(1),
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7 << 6, 6 << 6);
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/* Enable VMMC */
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mc13xxx_set_bits(mc13xxx, MC13783_REG_REG_MODE(1),
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1 << 18, 1 << 18);
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}
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/* Wait for required power level to run the CPU at 400 MHz */
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mdelay(100);
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console_flush();
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writel(CSCR_VAL_FINAL, MX27_CCM_BASE_ADDR + MX27_CSCR);
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writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0);
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writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1);
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/* Clocks have changed. Notify clients */
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clock_notifier_call_chain();
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/* Clock gating enable */
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writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR);
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imx_bbu_external_nand_register_handler("nand", "/dev/nand0.boot",
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bbu_nand_flags);
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imx_bbu_external_nor_register_handler("nor", "/dev/nor0.boot",
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bbu_nor_flags);
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defaultenv_append_directory(defaultenv_pcm038);
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return 0;
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}
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device_initcall(pcm038_init);
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