125 lines
3.0 KiB
C
125 lines
3.0 KiB
C
/*
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* Copyright 2012 GE Intelligent Platforms, Inc.
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*
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* Copyright 2007-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2003 Motorola Inc.
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* Modified by Xianghua Xiao, X.Xiao@motorola.com
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/processor.h>
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#include <asm/fsl_law.h>
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#include <mach/mpc85xx.h>
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#include <mach/mmu.h>
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#include <mach/immap_85xx.h>
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static void fsl_setup_ccsrbar(void)
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{
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u32 temp;
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u32 mas0, mas1, mas2, mas3, mas7;
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u32 *ccsr_virt = (u32 *)(CFG_CCSRBAR + 0x1000);
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mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
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mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
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mas2 = FSL_BOOKE_MAS2(CFG_CCSRBAR + 0x1000, MAS2_I|MAS2_G);
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mas3 = FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR);
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mas7 = FSL_BOOKE_MAS7(CFG_CCSRBAR_DEFAULT);
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e500_write_tlb(mas0, mas1, mas2, mas3, mas7);
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temp = in_be32(ccsr_virt);
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out_be32(ccsr_virt, CFG_CCSRBAR_PHYS >> 12);
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temp = in_be32((u32 *)CFG_CCSRBAR);
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}
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int fsl_l2_cache_init(void)
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{
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void __iomem *l2cache = (void __iomem *)MPC85xx_L2_ADDR;
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uint cache_ctl;
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uint svr, ver;
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u32 l2siz_field;
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svr = get_svr();
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ver = SVR_SOC_VER(svr);
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asm("msync;isync");
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cache_ctl = in_be32(l2cache + MPC85xx_L2_CTL_OFFSET);
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l2siz_field = (cache_ctl >> 28) & 0x3;
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switch (l2siz_field) {
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case 0x0:
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return -1;
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break;
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case 0x1:
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cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, L2SRAM=0 */
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break;
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case 0x2:
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/* set L2E=1, L2I=1, & L2SRAM=0 */
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cache_ctl = 0xc0000000;
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break;
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case 0x3:
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/* set L2E=1, L2I=1, & L2SRAM=0 */
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cache_ctl = 0xc0000000;
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break;
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}
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if (!(in_be32(l2cache + MPC85xx_L2_CTL_OFFSET) & MPC85xx_L2CTL_L2E)) {
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asm("msync;isync");
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/* invalidate & enable */
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out_be32(l2cache + MPC85xx_L2_CTL_OFFSET, cache_ctl);
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asm("msync;isync");
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}
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return 0;
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}
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void cpu_init_early_f(void)
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{
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u32 mas0, mas1, mas2, mas3, mas7;
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mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0);
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mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
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mas2 = FSL_BOOKE_MAS2(CFG_CCSRBAR, MAS2_I|MAS2_G);
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mas3 = FSL_BOOKE_MAS3(CFG_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
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mas7 = FSL_BOOKE_MAS7(CFG_CCSRBAR_PHYS);
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e500_write_tlb(mas0, mas1, mas2, mas3, mas7);
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/* set up CCSR if we want it moved */
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if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS)
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fsl_setup_ccsrbar();
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fsl_init_laws();
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e500_invalidate_tlb(1);
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e500_init_tlbs();
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}
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static int cpu_init_r(void)
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{
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e500_disable_tlb(14);
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e500_disable_tlb(15);
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return 0;
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}
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core_initcall(cpu_init_r);
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