307 lines
11 KiB
C
307 lines
11 KiB
C
/*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/omap2420.h>
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#include <asm/io.h>
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#include <asm/arch/bits.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/clocks.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/sys_info.h>
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/************************************************************
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* sdelay() - simple spin loop. Will be constant time as
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* its generally used in 12MHz bypass conditions only. This
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* is necessary until timers are accessible.
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*
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* not inline to increase chances its in cache when called
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*************************************************************/
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void sdelay (unsigned long loops)
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{
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0" (loops));
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}
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/*********************************************************************************
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* prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
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* -- called from SRAM, or Flash (using temp SRAM stack).
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*********************************************************************************/
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void prcm_init(void)
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{
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u32 rev,div;
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#ifdef CONFIG_PARTIAL_SRAM
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void (*f_lock_pll) (u32, u32, u32, u32);
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extern void *_end_vect, *_start;
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f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE);
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#endif
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__raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */
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__raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */
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__raw_writel(0, CM_ICLKEN1_CORE);
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__raw_writel(0, CM_ICLKEN2_CORE);
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__raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */
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__raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */
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__raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */
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__raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */
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rev = get_cpu_rev();
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if (rev == CPU_2420_ES1 || rev == CPU_2422_ES1)
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div = BUS_DIV_ES1;
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else
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div = BUS_DIV;
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__raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */
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sdelay(1000);
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#ifndef CONFIG_PARTIAL_SRAM
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/* If running fully from SRAM this is OK. The Flash bus drops out for just a little.
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* but then comes back. If running from Flash this sequence kills you, thus you need
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* to run it using CONFIG_PARTIAL_SRAM.
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*/
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__raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */
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wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */
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/* set clock selection and dpll dividers. */
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__raw_writel(DPLL_VAL, CM_CLKSEL1_PLL); /* set pll for target rate */
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__raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */
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sdelay(10000);
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__raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */
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sdelay(10000);
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wait_on_value(BIT0|BIT1, BIT2, CM_IDLEST_CKGEN, LDELAY); /*wait for dpll lock */
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#else
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/* if running from flash, need to jump to small relocated code area in SRAM.
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* This is the only safe spot to do configurations from.
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*/
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(*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN);
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#endif
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__raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */
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wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY); /* wait for apll lock */
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sdelay(1000);
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}
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/***********************************************
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* memif_init() - init the gpmc and sdrc
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* - early init routines, called from flash or
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* SRAM.
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***********************************************/
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void memif_init(void)
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{
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sdrc_init();
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#ifndef CONFIG_PARTIAL_SRAM /* don't init if calling from flash */
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gpmc_init();
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#endif
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}
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/********************************************************
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* mem_ok() - test used to see if timings are correct
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* for a part. Helps in gussing which part
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* we are currently using.
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*******************************************************/
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u32 mem_ok(void)
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{ u32 val;
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__raw_writel(0x0,OMAP2420_SDRC_CS0+0x400); /* clear pos A */
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__raw_writel(0x12345678, OMAP2420_SDRC_CS0);/* pattern to pos B */
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val = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */
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if (val != 0) /* see if pos A value changed*/
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return(0);
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else
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return(1);
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}
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/********************************************************
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* sdrc_init() - init the sdrc chip selects CS0 and CS1
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* - early init routines, called from flash or
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* SRAM.
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*******************************************************/
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void sdrc_init(void)
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{
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#define EARLY_INIT 1
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do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); /* only init up first bank here */
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}
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/**********************************************************
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* do_sdrc_init(): initialize the SDRAM for use.
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* -called from low level code with stack only.
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* -code sets up SDRAM timing and muxing for 2422 or 2420.
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* -optimal settings can be placed here, or redone after i2c
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* inspection of board info
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*
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* !!! When ES1 comes out need to conditionalize RFR value!!!
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**********************************************************/
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void do_sdrc_init(u32 offset, u32 early)
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{
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u32 cpu, bug=0, rev, shared=0, cs0=0, pmask=0,first=1;
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sdrc_data_t *sdata; /* do not change type */
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static const sdrc_data_t sdrc_2422 =
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{
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H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0, H4_2422_SDRC_ACTIM_CTRLA_0,
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H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL_ES1, H4_2422_SDRC_MR_0,
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H4_2422_SDRC_DLLA_CTRL, H4_2422_SDRC_DLLB_CTRL
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};
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static const sdrc_data_t sdrc_2420 =
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{
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H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0, H4_2420_SDRC_ACTIM_CTRLA_0,
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H4_2420_SDRC_ACTIM_CTRLB_0, H4_2420_SDRC_RFR_CTRL_ES1, H4_2420_SDRC_MR_0,
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H4_2420_SDRC_DLLA_CTRL, H4_2420_SDRC_DLLB_CTRL
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};
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if (offset == SDRC_CS0_OSET)
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cs0 = shared = 1; /* int regs shared between both chip select */
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cpu = get_cpu_type();
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/* warning generated, though code generation is correct. this may bite later, but is ok for now.
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* there is only so much C code you can do on stack only operation.
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*/
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if (cpu == CPU_2422)
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sdata = &sdrc_2422;
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else
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sdata = &sdrc_2420;
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__asm__ __volatile__("": : :"memory");
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#ifdef CONFIG_PARTIAL_SRAM
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/* u-boot is compiled to run in DDR at 8xxxxxxx. If we use data here which is not pc relative
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* we need to get the address correct. We need to find the current flash mapping to dress up
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* the initial pointer load. As long as this is const data we should be ok.
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*/
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if(early)
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sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base());
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#endif
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men_combo:
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if (!early && get_mem_type() == DDR_COMBO) { /* combo part has a shared CKE signal, can't use feature */
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pmask = BIT2;
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first = 0; /* trigger ddr_combo init */
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}
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if (shared) {
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__raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG);
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__raw_writel(SMART_IDLE|SOFTRESET, SDRC_SYSCONFIG); /* reset sdrc */
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wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */
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__raw_writel(SMART_IDLE, SDRC_SYSCONFIG); /* clear soft reset */
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__raw_writel(sdata->sdrc_sharing, SDRC_SHARING);
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__raw_writel((__raw_readl(SDRC_POWER)|SMART_IDLE) & ~pmask, SDRC_POWER);
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}
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if (first)
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__raw_writel(sdata->sdrc_mdcfg_0, SDRC_MCFG_0+offset);
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else {
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__raw_writel((__raw_readl(SDRC_POWER)|SMART_IDLE) & ~pmask, SDRC_POWER);
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__raw_writel(H4_2420_COMBO_MDCFG_0,SDRC_MCFG_0+offset);
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}
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if (cs0) {
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__raw_writel(sdata->sdrc_actim_ctrla_0, SDRC_ACTIM_CTRLA_0);
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__raw_writel(sdata->sdrc_actim_ctrlb_0, SDRC_ACTIM_CTRLB_0);
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} else {
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__raw_writel(sdata->sdrc_actim_ctrla_0, SDRC_ACTIM_CTRLA_1);
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__raw_writel(sdata->sdrc_actim_ctrlb_0, SDRC_ACTIM_CTRLB_1);
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}
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__raw_writel(sdata->sdrc_rfr_ctrl, SDRC_RFR_CTRL+offset);
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/* init sequence for _mDDR_ using manual commands (DDR is a bit different) */
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__raw_writel(CMD_NOP, SDRC_MANUAL_0+offset);
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sdelay(5000); /* susposed to be 100us per design spec for mddr*/
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__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0+offset);
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__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
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__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
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/*
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* CSx SDRC Mode Register
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* Burst length = 4 - DDR memory
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* Serial mode
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* CAS latency = x
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*/
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__raw_writel(sdata->sdrc_mr_0, SDRC_MR_0+offset);
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/* NOTE: ES1 242x _BUG_ DLL */
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rev = get_cpu_rev();
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if (rev == CPU_2420_ES1 || rev == CPU_2422_ES1)
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bug = BIT0;
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/* enable & load up DLL with good value for 75MHz, and set phase to 90% */
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if (shared) {
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__raw_writel(sdata->sdrc_dlla_ctrl, SDRC_DLLA_CTRL);
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__raw_writel(sdata->sdrc_dlla_ctrl & ~(BIT2|bug), SDRC_DLLA_CTRL);
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__raw_writel(sdata->sdrc_dllb_ctrl, SDRC_DLLB_CTRL);
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__raw_writel(sdata->sdrc_dllb_ctrl & ~(BIT2|bug) , SDRC_DLLB_CTRL);
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}
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sdelay(9000);
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if (!first || mem_ok()) /* passed test or 2nd bank init */
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return;
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else {
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first = 0;
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goto men_combo;
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}
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}
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/*****************************************************
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* gpmc_init(): init gpmc bus
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* Init GPMC for x16, MuxMode (SDRAM in x32).
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* This code can only be executed from SRAM or SDRAM.
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*****************************************************/
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void gpmc_init(void)
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{
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u32 mux=0, mtype, mwidth;
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/* global settings */
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__raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
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__raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
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__raw_writel(0x1, GPMC_TIMEOUT_CONTROL);/* timeout disable */
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__raw_writel(0x111, GPMC_CONFIG); /* set nWP, disable limited addr */
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/* discover bus connection from sysboot */
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if (is_gpmc_muxed() == GPMC_MUXED)
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mux = BIT9;
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mtype = get_gpmc0_type();
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mwidth = get_gpmc0_width();
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/* setup cs0 */
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__raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
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sdelay(1000);
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__raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0);
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//__raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
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__raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
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__raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
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//__raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
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__raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */
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sdelay(2000);
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/* setup cs1 */
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__raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
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sdelay(1000);
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__raw_writel(H4_24XX_GPMC_CONFIG1_1|mux, GPMC_CONFIG1_1);
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__raw_writel(H4_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
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__raw_writel(H4_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
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__raw_writel(H4_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
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__raw_writel(H4_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
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__raw_writel(H4_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
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__raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */
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sdelay(2000);
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}
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