449 lines
16 KiB
C
449 lines
16 KiB
C
#ifndef _SEQUENCER_H_
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#define _SEQUENCER_H_
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/*
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Copyright (c) 2012, Altera Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Altera Corporation nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define MRS_MIRROR_PING_PONG_ATSO 0
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#define DYNAMIC_CALIBRATION_MODE 0
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#define STATIC_QUICK_CALIBRATION 0
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#define DISABLE_GUARANTEED_READ 0
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#define STATIC_SKIP_CALIBRATION 0
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#if ENABLE_ASSERT
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#define ERR_IE_TEXT "Internal Error: Sub-system: %s, File: %s, Line: %d\n%s%s"
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#define ALTERA_INTERNAL_ERROR(string) \
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{err_report_internal_error(string, "SEQ", __FILE__, __LINE__); \
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exit(-1); }
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#define ALTERA_ASSERT(condition) \
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if (!(condition)) {\
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ALTERA_INTERNAL_ERROR(#condition); }
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#define ALTERA_INFO_ASSERT(condition, text) \
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if (!(condition)) {\
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ALTERA_INTERNAL_ERROR(text); }
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#else
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#define ALTERA_ASSERT(condition)
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#define ALTERA_INFO_ASSERT(condition, text)
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#endif
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#if RLDRAMII
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#define RW_MGR_NUM_DM_PER_WRITE_GROUP (1)
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#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (1)
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#else
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#define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH \
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/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
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#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH \
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/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
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#endif
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#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
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#define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
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#define RW_MGR_RUN_SINGLE_GROUP BASE_RW_MGR
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#define RW_MGR_RUN_ALL_GROUPS BASE_RW_MGR + 0x0400
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#define RW_MGR_DI_BASE (BASE_RW_MGR + 0x0020)
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#if DDR3
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#define DDR3_MR1_ODT_MASK 0xFFFFFD99
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#define DDR3_MR2_ODT_MASK 0xFFFFF9FF
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#define DDR3_AC_MIRR_MASK 0x020A8
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#endif /* DDR3 */
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#define RW_MGR_LOAD_CNTR_0 BASE_RW_MGR + 0x0800
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#define RW_MGR_LOAD_CNTR_1 BASE_RW_MGR + 0x0804
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#define RW_MGR_LOAD_CNTR_2 BASE_RW_MGR + 0x0808
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#define RW_MGR_LOAD_CNTR_3 BASE_RW_MGR + 0x080C
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#define RW_MGR_LOAD_JUMP_ADD_0 BASE_RW_MGR + 0x0C00
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#define RW_MGR_LOAD_JUMP_ADD_1 BASE_RW_MGR + 0x0C04
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#define RW_MGR_LOAD_JUMP_ADD_2 BASE_RW_MGR + 0x0C08
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#define RW_MGR_LOAD_JUMP_ADD_3 BASE_RW_MGR + 0x0C0C
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#define RW_MGR_RESET_READ_DATAPATH BASE_RW_MGR + 0x1000
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#define RW_MGR_SOFT_RESET BASE_RW_MGR + 0x2000
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#define RW_MGR_SET_CS_AND_ODT_MASK BASE_RW_MGR + 0x1400
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#define RW_MGR_SET_ACTIVE_RANK BASE_RW_MGR + 0x2400
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#define RW_MGR_LOOPBACK_MODE BASE_RW_MGR + 0x0200
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#define RW_MGR_RANK_NONE 0xFF
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#define RW_MGR_RANK_ALL 0x00
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#define RW_MGR_ODT_MODE_OFF 0
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#define RW_MGR_ODT_MODE_READ_WRITE 1
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#define NUM_CALIB_REPEAT 1
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#define NUM_READ_TESTS 7
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#define NUM_READ_PB_TESTS 7
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#define NUM_WRITE_TESTS 15
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#define NUM_WRITE_PB_TESTS 31
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#define PASS_ALL_BITS 1
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#define PASS_ONE_BIT 0
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/* calibration stages */
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#define CAL_STAGE_NIL 0
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#define CAL_STAGE_VFIFO 1
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#define CAL_STAGE_WLEVEL 2
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#define CAL_STAGE_LFIFO 3
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#define CAL_STAGE_WRITES 4
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#define CAL_STAGE_FULLTEST 5
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#define CAL_STAGE_REFRESH 6
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#define CAL_STAGE_CAL_SKIPPED 7
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#define CAL_STAGE_CAL_ABORTED 8
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#define CAL_STAGE_VFIFO_AFTER_WRITES 9
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/* calibration substages */
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#define CAL_SUBSTAGE_NIL 0
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#define CAL_SUBSTAGE_GUARANTEED_READ 1
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#define CAL_SUBSTAGE_DQS_EN_PHASE 2
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#define CAL_SUBSTAGE_VFIFO_CENTER 3
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#define CAL_SUBSTAGE_WORKING_DELAY 1
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#define CAL_SUBSTAGE_LAST_WORKING_DELAY 2
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#define CAL_SUBSTAGE_WLEVEL_COPY 3
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#define CAL_SUBSTAGE_WRITES_CENTER 1
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#define CAL_SUBSTAGE_READ_LATENCY 1
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#define CAL_SUBSTAGE_REFRESH 1
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#define MAX_RANKS (RW_MGR_MEM_NUMBER_OF_RANKS)
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#define MAX_DQS (RW_MGR_MEM_IF_WRITE_DQS_WIDTH > \
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RW_MGR_MEM_IF_READ_DQS_WIDTH ? \
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RW_MGR_MEM_IF_WRITE_DQS_WIDTH : \
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RW_MGR_MEM_IF_READ_DQS_WIDTH)
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#define MAX_DQ (RW_MGR_MEM_DATA_WIDTH)
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#define MAX_DM (RW_MGR_MEM_DATA_MASK_WIDTH)
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/* length of VFIFO, from SW_MACROS */
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#define VFIFO_SIZE (READ_VALID_FIFO_SIZE)
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/* Memory for data transfer between TCL scripts and NIOS.
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*
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* - First word is a command request.
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* - The remaining words are part of the transfer.
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*/
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#define BASE_PTR_MGR SEQUENCER_PTR_MGR_INST_BASE
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#define BASE_PHY_MGR SDR_PHYGRP_PHYMGRGRP_ADDRESS
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#define BASE_RW_MGR SDR_PHYGRP_RWMGRGRP_ADDRESS
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#define BASE_DATA_MGR SDR_PHYGRP_DATAMGRGRP_ADDRESS
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#define BASE_SCC_MGR SDR_PHYGRP_SCCGRP_ADDRESS
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#define BASE_REG_FILE SDR_PHYGRP_REGFILEGRP_ADDRESS
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#define BASE_TIMER SEQUENCER_TIMER_INST_BASE
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#define BASE_MMR SDR_CTRLGRP_ADDRESS
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#define BASE_TRK_MGR (0x000D0000)
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/* Register file addresses. */
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#define REG_FILE_SIGNATURE (BASE_REG_FILE + 0x0000)
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#define REG_FILE_DEBUG_DATA_ADDR (BASE_REG_FILE + 0x0004)
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#define REG_FILE_CUR_STAGE (BASE_REG_FILE + 0x0008)
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#define REG_FILE_FOM (BASE_REG_FILE + 0x000C)
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#define REG_FILE_FAILING_STAGE (BASE_REG_FILE + 0x0010)
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#define REG_FILE_DEBUG1 (BASE_REG_FILE + 0x0014)
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#define REG_FILE_DEBUG2 (BASE_REG_FILE + 0x0018)
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#define REG_FILE_DTAPS_PER_PTAP (BASE_REG_FILE + 0x001C)
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#define REG_FILE_TRK_SAMPLE_COUNT (BASE_REG_FILE + 0x0020)
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#define REG_FILE_TRK_LONGIDLE (BASE_REG_FILE + 0x0024)
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#define REG_FILE_DELAYS (BASE_REG_FILE + 0x0028)
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#define REG_FILE_TRK_RW_MGR_ADDR (BASE_REG_FILE + 0x002C)
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#define REG_FILE_TRK_READ_DQS_WIDTH (BASE_REG_FILE + 0x0030)
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#define REG_FILE_TRK_RFSH (BASE_REG_FILE + 0x0034)
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/* PHY manager configuration registers. */
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#define PHY_MGR_PHY_RLAT (BASE_PHY_MGR + 0x40 + 0x00)
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#define PHY_MGR_RESET_MEM_STBL (BASE_PHY_MGR + 0x40 + 0x04)
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#define PHY_MGR_MUX_SEL (BASE_PHY_MGR + 0x40 + 0x08)
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#define PHY_MGR_CAL_STATUS (BASE_PHY_MGR + 0x40 + 0x0c)
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#define PHY_MGR_CAL_DEBUG_INFO (BASE_PHY_MGR + 0x40 + 0x10)
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#define PHY_MGR_VFIFO_RD_EN_OVRD (BASE_PHY_MGR + 0x40 + 0x14)
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#if CALIBRATE_BIT_SLIPS
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#define PHY_MGR_FR_SHIFT (BASE_PHY_MGR + 0x40 + 0x20)
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#if MULTIPLE_AFI_WLAT
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#define PHY_MGR_AFI_WLAT (BASE_PHY_MGR + 0x40 + 0x20 + 4 * \
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RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
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#else
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#define PHY_MGR_AFI_WLAT (BASE_PHY_MGR + 0x40 + 0x18)
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#endif
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#else
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#define PHY_MGR_AFI_WLAT (BASE_PHY_MGR + 0x40 + 0x18)
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#endif
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#define PHY_MGR_AFI_RLAT (BASE_PHY_MGR + 0x40 + 0x1c)
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#define PHY_MGR_CAL_RESET (0)
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#define PHY_MGR_CAL_SUCCESS (1)
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#define PHY_MGR_CAL_FAIL (2)
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/* PHY manager command addresses. */
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#define PHY_MGR_CMD_INC_VFIFO_FR (BASE_PHY_MGR + 0x0000)
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#define PHY_MGR_CMD_INC_VFIFO_HR (BASE_PHY_MGR + 0x0004)
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#define PHY_MGR_CMD_INC_VFIFO_HARD_PHY (BASE_PHY_MGR + 0x0004)
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#define PHY_MGR_CMD_FIFO_RESET (BASE_PHY_MGR + 0x0008)
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#define PHY_MGR_CMD_INC_VFIFO_FR_HR (BASE_PHY_MGR + 0x000C)
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#define PHY_MGR_CMD_INC_VFIFO_QR (BASE_PHY_MGR + 0x0010)
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/* PHY manager parameters. */
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#define PHY_MGR_MAX_RLAT_WIDTH (BASE_PHY_MGR + 0x0000)
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#define PHY_MGR_MAX_AFI_WLAT_WIDTH (BASE_PHY_MGR + 0x0004)
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#define PHY_MGR_MAX_AFI_RLAT_WIDTH (BASE_PHY_MGR + 0x0008)
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#define PHY_MGR_CALIB_SKIP_STEPS (BASE_PHY_MGR + 0x000c)
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#define PHY_MGR_CALIB_VFIFO_OFFSET (BASE_PHY_MGR + 0x0010)
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#define PHY_MGR_CALIB_LFIFO_OFFSET (BASE_PHY_MGR + 0x0014)
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#define PHY_MGR_RDIMM (BASE_PHY_MGR + 0x0018)
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#define PHY_MGR_MEM_T_WL (BASE_PHY_MGR + 0x001c)
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#define PHY_MGR_MEM_T_RL (BASE_PHY_MGR + 0x0020)
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/* Data Manager */
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#define DATA_MGR_DRAM_CFG (BASE_DATA_MGR + 0x0000)
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#define DATA_MGR_MEM_T_WL (BASE_DATA_MGR + 0x0004)
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#define DATA_MGR_MEM_T_ADD (BASE_DATA_MGR + 0x0008)
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#define DATA_MGR_MEM_T_RL (BASE_DATA_MGR + 0x000C)
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#define DATA_MGR_MEM_T_RFC (BASE_DATA_MGR + 0x0010)
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#define DATA_MGR_MEM_T_REFI (BASE_DATA_MGR + 0x0014)
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#define DATA_MGR_MEM_T_WR (BASE_DATA_MGR + 0x0018)
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#define DATA_MGR_MEM_T_MRD (BASE_DATA_MGR + 0x001C)
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#define DATA_MGR_COL_WIDTH (BASE_DATA_MGR + 0x0020)
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#define DATA_MGR_ROW_WIDTH (BASE_DATA_MGR + 0x0024)
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#define DATA_MGR_BANK_WIDTH (BASE_DATA_MGR + 0x0028)
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#define DATA_MGR_CS_WIDTH (BASE_DATA_MGR + 0x002C)
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#define DATA_MGR_ITF_WIDTH (BASE_DATA_MGR + 0x0030)
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#define DATA_MGR_DVC_WIDTH (BASE_DATA_MGR + 0x0034)
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#define MEM_T_WL_ADD DATA_MGR_MEM_T_WL
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#define MEM_T_RL_ADD DATA_MGR_MEM_T_RL
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#define CALIB_SKIP_DELAY_LOOPS (1 << 0)
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#define CALIB_SKIP_ALL_BITS_CHK (1 << 1)
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#define CALIB_SKIP_DELAY_SWEEPS (1 << 2)
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#define CALIB_SKIP_VFIFO (1 << 3)
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#define CALIB_SKIP_LFIFO (1 << 4)
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#define CALIB_SKIP_WLEVEL (1 << 5)
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#define CALIB_SKIP_WRITES (1 << 6)
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#define CALIB_SKIP_FULL_TEST (1 << 7)
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#define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \
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CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
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CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
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#define CALIB_IN_RTL_SIM (1 << 8)
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/* Scan chain manager command addresses */
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#define WRITE_SCC_DQS_IN_DELAY(group, delay) \
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IOWR_32DIRECT(SCC_MGR_DQS_IN_DELAY, (group) << 2, delay)
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#define WRITE_SCC_DQS_EN_DELAY(group, delay) \
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IOWR_32DIRECT(SCC_MGR_DQS_EN_DELAY, (group) << 2, (delay) \
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+ IO_DQS_EN_DELAY_OFFSET)
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#define WRITE_SCC_DQS_EN_PHASE(group, phase) \
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IOWR_32DIRECT(SCC_MGR_DQS_EN_PHASE, (group) << 2, phase)
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#define WRITE_SCC_DQDQS_OUT_PHASE(group, phase) \
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IOWR_32DIRECT(SCC_MGR_DQDQS_OUT_PHASE, (group) << 2, phase)
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#define WRITE_SCC_OCT_OUT1_DELAY(group, delay) \
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IOWR_32DIRECT(SCC_MGR_OCT_OUT1_DELAY, (group) << 2, delay)
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#define WRITE_SCC_OCT_OUT2_DELAY(group, delay)
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#define WRITE_SCC_DQS_BYPASS(group, bypass)
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#define WRITE_SCC_DQ_OUT1_DELAY(pin, delay) \
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IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (pin) << 2, delay)
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#define WRITE_SCC_DQ_OUT2_DELAY(pin, delay)
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#define WRITE_SCC_DQ_IN_DELAY(pin, delay) \
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IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, (pin) << 2, delay)
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#define WRITE_SCC_DQ_BYPASS(pin, bypass)
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#define WRITE_SCC_RFIFO_MODE(pin, mode)
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#define WRITE_SCC_HHP_EXTRAS(value) \
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IOWR_32DIRECT(SCC_MGR_HHP_GLOBALS, SCC_MGR_HHP_EXTRAS_OFFSET, value)
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#define WRITE_SCC_HHP_DQSE_MAP(value) \
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IOWR_32DIRECT(SCC_MGR_HHP_GLOBALS, SCC_MGR_HHP_DQSE_MAP_OFFSET, value)
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#define WRITE_SCC_DQS_IO_OUT1_DELAY(delay) \
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IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, \
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(RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2, delay)
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#define WRITE_SCC_DQS_IO_OUT2_DELAY(delay)
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#define WRITE_SCC_DQS_IO_IN_DELAY(delay) \
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IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, \
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(RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2, delay)
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#define WRITE_SCC_DM_IO_OUT1_DELAY(pin, delay) \
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IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, \
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(RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2, delay)
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#define WRITE_SCC_DM_IO_OUT2_DELAY(pin, delay)
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#define WRITE_SCC_DM_IO_IN_DELAY(pin, delay) \
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IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, \
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(RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2, delay)
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#define WRITE_SCC_DM_BYPASS(pin, bypass)
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#define READ_SCC_DQS_IN_DELAY(group) \
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IORD_32DIRECT(SCC_MGR_DQS_IN_DELAY, (group) << 2)
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#define READ_SCC_DQS_EN_DELAY(group) \
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(IORD_32DIRECT(SCC_MGR_DQS_EN_DELAY, (group) << 2) \
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- IO_DQS_EN_DELAY_OFFSET)
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#define READ_SCC_DQS_EN_PHASE(group) \
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IORD_32DIRECT(SCC_MGR_DQS_EN_PHASE, (group) << 2)
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#define READ_SCC_DQDQS_OUT_PHASE(group) \
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IORD_32DIRECT(SCC_MGR_DQDQS_OUT_PHASE, (group) << 2)
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#define READ_SCC_OCT_OUT1_DELAY(group) \
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IORD_32DIRECT(SCC_MGR_OCT_OUT1_DELAY, \
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(group * RW_MGR_MEM_IF_READ_DQS_WIDTH / \
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RW_MGR_MEM_IF_WRITE_DQS_WIDTH) << 2)
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#define READ_SCC_OCT_OUT2_DELAY(group) 0
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#define READ_SCC_DQS_BYPASS(group) 0
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#define READ_SCC_DQS_BYPASS(group) 0
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#define READ_SCC_DQ_OUT1_DELAY(pin) \
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IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (pin) << 2)
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#define READ_SCC_DQ_OUT2_DELAY(pin) 0
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#define READ_SCC_DQ_IN_DELAY(pin) \
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IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, (pin) << 2)
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#define READ_SCC_DQ_BYPASS(pin) 0
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#define READ_SCC_RFIFO_MODE(pin) 0
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#define READ_SCC_DQS_IO_OUT1_DELAY() \
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IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, \
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(RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2)
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#define READ_SCC_DQS_IO_OUT2_DELAY() 0
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#define READ_SCC_DQS_IO_IN_DELAY() \
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IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, \
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(RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2)
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#define READ_SCC_DM_IO_OUT1_DELAY(pin) \
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IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, \
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(RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2)
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#define READ_SCC_DM_IO_OUT2_DELAY(pin) 0
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#define READ_SCC_DM_IO_IN_DELAY(pin) \
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IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, \
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(RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2)
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#define READ_SCC_DM_BYPASS(pin) 0
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#define SCC_MGR_GROUP_COUNTER (BASE_SCC_MGR + 0x0000)
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#define SCC_MGR_DQS_IN_DELAY (BASE_SCC_MGR + 0x0100)
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#define SCC_MGR_DQS_EN_PHASE (BASE_SCC_MGR + 0x0200)
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#define SCC_MGR_DQS_EN_DELAY (BASE_SCC_MGR + 0x0300)
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#define SCC_MGR_DQDQS_OUT_PHASE (BASE_SCC_MGR + 0x0400)
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#define SCC_MGR_OCT_OUT1_DELAY (BASE_SCC_MGR + 0x0500)
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#define SCC_MGR_IO_OUT1_DELAY (BASE_SCC_MGR + 0x0700)
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#define SCC_MGR_IO_IN_DELAY (BASE_SCC_MGR + 0x0900)
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/* HHP-HPS-specific versions of some commands */
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#define SCC_MGR_DQS_EN_DELAY_GATE (BASE_SCC_MGR + 0x0600)
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#define SCC_MGR_IO_OE_DELAY (BASE_SCC_MGR + 0x0800)
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#define SCC_MGR_HHP_GLOBALS (BASE_SCC_MGR + 0x0A00)
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#define SCC_MGR_HHP_RFILE (BASE_SCC_MGR + 0x0B00)
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/* HHP-HPS-specific values */
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#define SCC_MGR_HHP_EXTRAS_OFFSET 0
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#define SCC_MGR_HHP_DQSE_MAP_OFFSET 1
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#define SCC_MGR_DQS_ENA (BASE_SCC_MGR + 0x0E00)
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#define SCC_MGR_DQS_IO_ENA (BASE_SCC_MGR + 0x0E04)
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#define SCC_MGR_DQ_ENA (BASE_SCC_MGR + 0x0E08)
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#define SCC_MGR_DM_ENA (BASE_SCC_MGR + 0x0E0C)
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#define SCC_MGR_UPD (BASE_SCC_MGR + 0x0E20)
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#define SCC_MGR_ACTIVE_RANK (BASE_SCC_MGR + 0x0E40)
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#define SCC_MGR_AFI_CAL_INIT (BASE_SCC_MGR + 0x0D00)
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/* PHY Debug mode flag constants */
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#define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
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#define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
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#define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
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#define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
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#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
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#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
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/* Bitfield type changes depending on protocol */
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typedef uint32_t t_btfld;
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#define RW_MGR_INST_ROM_WRITE BASE_RW_MGR + 0x1800
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#define RW_MGR_AC_ROM_WRITE BASE_RW_MGR + 0x1C00
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/* parameter variable holder */
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typedef struct param_type {
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t_btfld read_correct_mask;
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t_btfld read_correct_mask_vg;
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t_btfld write_correct_mask;
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t_btfld write_correct_mask_vg;
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/* set a particular entry to 1 if we need to skip a particular group */
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} param_t;
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/* global variable holder */
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typedef struct gbl_type {
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uint32_t phy_debug_mode_flags;
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/* current read latency */
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uint32_t curr_read_lat;
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/* current write latency */
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uint32_t curr_write_lat;
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/* error code */
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uint32_t error_substage;
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uint32_t error_stage;
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uint32_t error_group;
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/* figure-of-merit in, figure-of-merit out */
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uint32_t fom_in;
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uint32_t fom_out;
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/*USER Number of RW Mgr NOP cycles between
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write command and write data */
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#if MULTIPLE_AFI_WLAT
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uint32_t rw_wl_nop_cycles_per_group[RW_MGR_MEM_IF_WRITE_DQS_WIDTH];
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#endif
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uint32_t rw_wl_nop_cycles;
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} gbl_t;
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#endif
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