209 lines
6.2 KiB
C
209 lines
6.2 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <init.h>
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#include <common.h>
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#include <io.h>
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#include <notifier.h>
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#include <sizes.h>
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#include <mach/imx5.h>
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#include <mach/imx-regs.h>
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#include <mach/clock-imx51_53.h>
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#define SI_REV 0x48
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static u32 mx53_silicon_revision;
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static char *mx53_rev_string = "unknown";
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int imx_silicon_revision(void)
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{
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return mx53_silicon_revision;
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}
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static int query_silicon_revision(void)
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{
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void __iomem *rom = MX53_IROM_BASE_ADDR;
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u32 rev;
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rev = readl(rom + SI_REV);
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switch (rev) {
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case 0x10:
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mx53_silicon_revision = IMX_CHIP_REV_1_0;
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mx53_rev_string = "1.0";
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break;
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case 0x20:
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mx53_silicon_revision = IMX_CHIP_REV_2_0;
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mx53_rev_string = "2.0";
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break;
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case 0x21:
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mx53_silicon_revision = IMX_CHIP_REV_2_1;
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mx53_rev_string = "2.1";
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break;
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default:
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mx53_silicon_revision = 0;
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}
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return 0;
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}
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core_initcall(query_silicon_revision);
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static int imx53_print_silicon_rev(void)
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{
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printf("detected i.MX53 rev %s\n", mx53_rev_string);
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return 0;
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}
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device_initcall(imx53_print_silicon_rev);
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static int imx53_init(void)
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{
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add_generic_device("imx_iim", 0, NULL, MX53_IIM_BASE_ADDR, SZ_4K,
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IORESOURCE_MEM, NULL);
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add_generic_device("imx53-ccm", 0, NULL, MX53_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpt", 0, NULL, 0X53fa0000, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 0, NULL, MX53_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 1, NULL, MX53_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 2, NULL, MX53_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 3, NULL, MX53_GPIO4_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 4, NULL, MX53_GPIO5_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 5, NULL, MX53_GPIO6_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 6, NULL, MX53_GPIO7_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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return 0;
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}
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postcore_initcall(imx53_init);
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#define setup_pll_1000(base) imx5_setup_pll((base), 1000, ((10 << 4) + ((1 - 1) << 0)), (12 - 1), 5)
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#define setup_pll_800(base) imx5_setup_pll((base), 800, ((8 << 4) + ((1 - 1) << 0)), (3 - 1), 1)
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#define setup_pll_400(base) imx5_setup_pll((base), 400, ((8 << 4) + ((2 - 1) << 0)), (3 - 1), 1)
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#define setup_pll_455(base) imx5_setup_pll((base), 455, ((9 << 4) + ((2 - 1) << 0)), (48 - 1), 23)
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#define setup_pll_216(base) imx5_setup_pll((base), 216, ((8 << 4) + ((2 - 1) << 0)), (1 - 1), 1)
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void imx53_init_lowlevel(unsigned int cpufreq_mhz)
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{
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void __iomem *ccm = (void __iomem *)MX53_CCM_BASE_ADDR;
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u32 r;
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imx5_init_lowlevel();
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/*
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* AIPS setup - Only setup MPROTx registers.
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* The PACR default values are good.
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, MX53_AIPS1_BASE_ADDR + 0);
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writel(0x77777777, MX53_AIPS1_BASE_ADDR + 4);
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writel(0x77777777, MX53_AIPS2_BASE_ADDR + 0);
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writel(0x77777777, MX53_AIPS2_BASE_ADDR + 4);
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/* Gate of clocks to the peripherals first */
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writel(0x3fffffff, ccm + MX5_CCM_CCGR0);
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writel(0x00000000, ccm + MX5_CCM_CCGR1);
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writel(0x00000000, ccm + MX5_CCM_CCGR2);
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writel(0x00000000, ccm + MX5_CCM_CCGR3);
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writel(0x00030000, ccm + MX5_CCM_CCGR4);
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writel(0x00fff030, ccm + MX5_CCM_CCGR5);
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writel(0x0f00030f, ccm + MX5_CCM_CCGR6);
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writel(0x00000000, ccm + MX53_CCM_CCGR7);
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/* Switch ARM to step clock */
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writel(0x4, ccm + MX5_CCM_CCSR);
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if (cpufreq_mhz == 1000)
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setup_pll_1000((void __iomem *)MX53_PLL1_BASE_ADDR);
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else
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setup_pll_800((void __iomem *)MX53_PLL1_BASE_ADDR);
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setup_pll_400((void __iomem *)MX53_PLL3_BASE_ADDR);
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/* Switch peripheral to PLL3 */
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writel(0x00015154, ccm + MX5_CCM_CBCMR);
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writel(0x02888945 | (1<<16), ccm + MX5_CCM_CBCDR);
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/* make sure change is effective */
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while (readl(ccm + MX5_CCM_CDHIPR));
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setup_pll_400((void __iomem *)MX53_PLL2_BASE_ADDR);
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/* Switch peripheral to PLL2 */
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r = 0x00808145 |
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(2 << 10) |
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(0 << 16) |
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(1 << 19);
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writel(r, ccm + MX5_CCM_CBCDR);
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writel(0x00016154, ccm + MX5_CCM_CBCMR);
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r = readl(ccm + MX5_CCM_CSCMR1);
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/* change uart clk parent to pll2 */
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r &= ~MX5_CCM_CSCMR1_UART_CLK_SEL_MASK;
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r |= 1 << MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
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/* USB phy clock from osc */
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r &= ~(1 << MX5_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET);
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writel(r, ccm + MX5_CCM_CSCMR1);
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/* make sure change is effective */
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while (readl(ccm + MX5_CCM_CDHIPR));
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setup_pll_216((void __iomem *)MX53_PLL3_BASE_ADDR);
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setup_pll_455((void __iomem *)MX53_PLL4_BASE_ADDR);
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/* Set the platform clock dividers */
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writel(0x00000124, MX53_ARM_BASE_ADDR + 0x14);
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writel(0, ccm + MX5_CCM_CACRR);
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/* Switch ARM back to PLL 1. */
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writel(0, ccm + MX5_CCM_CCSR);
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/* make uart div = 6*/
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r = readl(ccm + MX5_CCM_CSCDR1);
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r &= ~0x3f;
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r |= 0x0a;
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r &= ~MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK;
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r &= ~MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK;
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r |= 1 << MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET;
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r &= ~MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK;
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r &= ~MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK;
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r |= 1 << MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET;
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r &= ~MX5_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
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r &= ~MX5_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
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r |= 3 << MX5_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
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r |= 1 << MX5_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
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writel(r, ccm + MX5_CCM_CSCDR1);
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/* Restore the default values in the Gate registers */
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writel(0xffffffff, ccm + MX5_CCM_CCGR0);
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writel(0xffffffff, ccm + MX5_CCM_CCGR1);
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writel(0xffffffff, ccm + MX5_CCM_CCGR2);
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writel(0xffffffff, ccm + MX5_CCM_CCGR3);
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writel(0xffffffff, ccm + MX5_CCM_CCGR4);
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writel(0xffffffff, ccm + MX5_CCM_CCGR5);
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writel(0xffffffff, ccm + MX5_CCM_CCGR6);
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writel(0xffffffff, ccm + MX53_CCM_CCGR7);
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clock_notifier_call_chain();
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writel(0, ccm + MX5_CCM_CCDR);
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}
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